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yaml --- r: 213733 b: refs/heads/master c: b9ac41e h: refs/heads/master i: 213731: eea1db3 v: v3
git-mirror · Oct 22, 2010 · 84afd24 · 84afd24
1 parent adb70af
commit 84afd24
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Showing 2 changed files with 20 additions and 1 deletion.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: fec84d21c52bca67949a17aaf7d410b497f8e1b0
+refs/heads/master: b9ac41e314f0b43641bc01bd553fd2e0458ed832
diff --git a/trunk/arch/blackfin/include/asm/bfin5xx_spi.h b/trunk/arch/blackfin/include/asm/bfin5xx_spi.h
@@ -41,6 +41,25 @@
 #define BIT_STU_SENDOVER    0x0001
 #define BIT_STU_RECVFULL    0x0020
 
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin spi registers layout
+ */
+struct bfin_spi_regs {
+	__BFP(ctl);
+	__BFP(flg);
+	__BFP(stat);
+	__BFP(tdbr);
+	__BFP(rdbr);
+	__BFP(baud);
+	__BFP(shadow);
+};
+
 #define MAX_CTRL_CS          8  /* cs in spi controller */
 
 /* device.platform_data for SSP controller devices */