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52 changes: 52 additions & 0 deletions
52
Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
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| * AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin | ||
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| Required properties: | ||
| - compatible : Should be "jedec,lpddr2-timings" | ||
| - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32> | ||
| - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32> | ||
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| Optional properties: | ||
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| The following properties represent AC timing parameters from the memory | ||
| data-sheet of the device for a given speed-bin. All these properties are | ||
| of type <u32> and the default unit is ps (pico seconds). Parameters with | ||
| a different unit have a suffix indicating the unit such as 'tRAS-max-ns' | ||
| - tRCD | ||
| - tWR | ||
| - tRAS-min | ||
| - tRRD | ||
| - tWTR | ||
| - tXP | ||
| - tRTP | ||
| - tDQSCK-max | ||
| - tFAW | ||
| - tZQCS | ||
| - tZQinit | ||
| - tRPab | ||
| - tZQCL | ||
| - tCKESR | ||
| - tRAS-max-ns | ||
| - tDQSCK-max-derated | ||
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| Example: | ||
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| timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { | ||
| compatible = "jedec,lpddr2-timings"; | ||
| min-freq = <10000000>; | ||
| max-freq = <400000000>; | ||
| tRPab = <21000>; | ||
| tRCD = <18000>; | ||
| tWR = <15000>; | ||
| tRAS-min = <42000>; | ||
| tRRD = <10000>; | ||
| tWTR = <7500>; | ||
| tXP = <7500>; | ||
| tRTP = <7500>; | ||
| tCKESR = <15000>; | ||
| tDQSCK-max = <5500>; | ||
| tFAW = <50000>; | ||
| tZQCS = <90000>; | ||
| tZQCL = <360000>; | ||
| tZQinit = <1000000>; | ||
| tRAS-max-ns = <70000>; | ||
| }; |
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| * LPDDR2 SDRAM memories compliant to JEDEC JESD209-2 | ||
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| Required properties: | ||
| - compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2", | ||
| "jedec,lpddr2-s4" | ||
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| "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type | ||
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| "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type | ||
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| "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type | ||
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| - density : <u32> representing density in Mb (Mega bits) | ||
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| - io-width : <u32> representing bus width. Possible values are 8, 16, and 32 | ||
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| Optional properties: | ||
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| The following optional properties represent the minimum value of some AC | ||
| timing parameters of the DDR device in terms of number of clock cycles. | ||
| These values shall be obtained from the device data-sheet. | ||
| - tRRD-min-tck | ||
| - tWTR-min-tck | ||
| - tXP-min-tck | ||
| - tRTP-min-tck | ||
| - tCKE-min-tck | ||
| - tRPab-min-tck | ||
| - tRCD-min-tck | ||
| - tWR-min-tck | ||
| - tRASmin-min-tck | ||
| - tCKESR-min-tck | ||
| - tFAW-min-tck | ||
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| Child nodes: | ||
| - The lpddr2 node may have one or more child nodes of type "lpddr2-timings". | ||
| "lpddr2-timings" provides AC timing parameters of the device for | ||
| a given speed-bin. The user may provide the timings for as many | ||
| speed-bins as is required. Please see Documentation/devicetree/ | ||
| bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings" | ||
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| Example: | ||
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| elpida_ECB240ABACN : lpddr2 { | ||
| compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4"; | ||
| density = <2048>; | ||
| io-width = <32>; | ||
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| tRPab-min-tck = <3>; | ||
| tRCD-min-tck = <3>; | ||
| tWR-min-tck = <3>; | ||
| tRASmin-min-tck = <3>; | ||
| tRRD-min-tck = <2>; | ||
| tWTR-min-tck = <2>; | ||
| tXP-min-tck = <2>; | ||
| tRTP-min-tck = <2>; | ||
| tCKE-min-tck = <3>; | ||
| tCKESR-min-tck = <3>; | ||
| tFAW-min-tck = <8>; | ||
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| timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { | ||
| compatible = "jedec,lpddr2-timings"; | ||
| min-freq = <10000000>; | ||
| max-freq = <400000000>; | ||
| tRPab = <21000>; | ||
| tRCD = <18000>; | ||
| tWR = <15000>; | ||
| tRAS-min = <42000>; | ||
| tRRD = <10000>; | ||
| tWTR = <7500>; | ||
| tXP = <7500>; | ||
| tRTP = <7500>; | ||
| tCKESR = <15000>; | ||
| tDQSCK-max = <5500>; | ||
| tFAW = <50000>; | ||
| tZQCS = <90000>; | ||
| tZQCL = <360000>; | ||
| tZQinit = <1000000>; | ||
| tRAS-max-ns = <70000>; | ||
| }; | ||
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| timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 { | ||
| compatible = "jedec,lpddr2-timings"; | ||
| min-freq = <10000000>; | ||
| max-freq = <200000000>; | ||
| tRPab = <21000>; | ||
| tRCD = <18000>; | ||
| tWR = <15000>; | ||
| tRAS-min = <42000>; | ||
| tRRD = <10000>; | ||
| tWTR = <10000>; | ||
| tXP = <7500>; | ||
| tRTP = <7500>; | ||
| tCKESR = <15000>; | ||
| tDQSCK-max = <5500>; | ||
| tFAW = <50000>; | ||
| tZQCS = <90000>; | ||
| tZQCL = <360000>; | ||
| tZQinit = <1000000>; | ||
| tRAS-max-ns = <70000>; | ||
| }; | ||
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| } |
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55
Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
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| * EMIF family of TI SDRAM controllers | ||
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| EMIF - External Memory Interface - is an SDRAM controller used in | ||
| TI SoCs. EMIF supports, based on the IP revision, one or more of | ||
| DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance | ||
| of the EMIF IP and memory parts attached to it. | ||
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| Required properties: | ||
| - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev> | ||
| is the IP revision of the specific EMIF instance. | ||
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| - phy-type : <u32> indicating the DDR phy type. Following are the | ||
| allowed values | ||
| <1> : Attila PHY | ||
| <2> : Intelli PHY | ||
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| - device-handle : phandle to a "lpddr2" node representing the memory part | ||
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| - ti,hwmods : For TI hwmods processing and omap device creation | ||
| the value shall be "emif<n>" where <n> is the number of the EMIF | ||
| instance with base 1. | ||
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| Optional properties: | ||
| - cs1-used : Have this property if CS1 of this EMIF | ||
| instance has a memory part attached to it. If there is a memory | ||
| part attached to CS1, it should be the same type as the one on CS0, | ||
| so there is no need to give the details of this memory part. | ||
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| - cal-resistor-per-cs : Have this property if the board has one | ||
| calibration resistor per chip-select. | ||
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| - hw-caps-read-idle-ctrl: Have this property if the controller | ||
| supports read idle window programming | ||
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| - hw-caps-dll-calib-ctrl: Have this property if the controller | ||
| supports dll calibration control | ||
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| - hw-caps-ll-interface : Have this property if the controller | ||
| has a low latency interface and corresponding interrupt events | ||
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| - hw-caps-temp-alert : Have this property if the controller | ||
| has capability for generating SDRAM temperature alerts | ||
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| Example: | ||
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| emif1: emif@0x4c000000 { | ||
| compatible = "ti,emif-4d"; | ||
| ti,hwmods = "emif2"; | ||
| phy-type = <1>; | ||
| device-handle = <&elpida_ECB240ABACN>; | ||
| cs1-used; | ||
| hw-caps-read-idle-ctrl; | ||
| hw-caps-ll-interface; | ||
| hw-caps-temp-alert; | ||
| }; |
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