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---
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yaml
---
r: 326771
b: refs/heads/master
c: 497ae17
h: refs/heads/master
i:
  326769: 5963bb5
  326767: 1660397
v: v3
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Shawn Guo committed Sep 11, 2012
1 parent fa1c1d8 commit 84ed085
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Showing 3 changed files with 51 additions and 2 deletions.
2 changes: 1 addition & 1 deletion [refs]
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---
refs/heads/master: 9e3c00665d915c4f5645d43aec5a943b5eee55de
refs/heads/master: 497ae1747b8c52fde4ab7e9987326ca43886b652
25 changes: 24 additions & 1 deletion trunk/arch/arm/boot/dts/imx6q-sabresd.dts
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Expand Up @@ -22,28 +22,51 @@
};

soc {

aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};

iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;

hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
};

aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};

usdhc@02194000 { /* uSDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};

usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
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26 changes: 26 additions & 0 deletions trunk/arch/arm/boot/dts/imx6q.dtsi
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Expand Up @@ -609,6 +609,15 @@
};
};

uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
>;
};
};

uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
Expand All @@ -627,6 +636,23 @@
};
};

usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
>;
};
};

usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
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