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drm/radeon: program auxch directly (v2)
The atombios tables have an unfortunate restriction on only being able to write 12 bytes, MST really wants 16-bytes here, and since the hw can do it, we should just write directly to it. This uses a module option to allow for it now, and maybe we should provide the old code as a fallback for a while. v2: (agd5f) - move registers to a proper register header - only enable on DCE5+ - enable by default on DCE5+ - Switch pad to aux mode before using it - reformat instance handling to better match the rest of the driver Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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/* | ||
* Copyright 2015 Red Hat Inc. | ||
* | ||
* Permission is hereby granted, free of charge, to any person obtaining a | ||
* copy of this software and associated documentation files (the "Software"), | ||
* to deal in the Software without restriction, including without limitation | ||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
* and/or sell copies of the Software, and to permit persons to whom the | ||
* Software is furnished to do so, subject to the following conditions: | ||
* | ||
* The above copyright notice and this permission notice shall be included in | ||
* all copies or substantial portions of the Software. | ||
* | ||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
* OTHER DEALINGS IN THE SOFTWARE. | ||
* | ||
* Authors: Dave Airlie | ||
*/ | ||
#include <drm/drmP.h> | ||
#include <drm/radeon_drm.h> | ||
#include "radeon.h" | ||
#include "nid.h" | ||
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#define AUX_RX_ERROR_FLAGS (AUX_SW_RX_OVERFLOW | \ | ||
AUX_SW_RX_HPD_DISCON | \ | ||
AUX_SW_RX_PARTIAL_BYTE | \ | ||
AUX_SW_NON_AUX_MODE | \ | ||
AUX_SW_RX_MIN_COUNT_VIOL | \ | ||
AUX_SW_RX_INVALID_STOP | \ | ||
AUX_SW_RX_SYNC_INVALID_L | \ | ||
AUX_SW_RX_SYNC_INVALID_H | \ | ||
AUX_SW_RX_INVALID_START | \ | ||
AUX_SW_RX_RECV_NO_DET | \ | ||
AUX_SW_RX_RECV_INVALID_H | \ | ||
AUX_SW_RX_RECV_INVALID_V) | ||
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||
#define AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f) | ||
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#define BARE_ADDRESS_SIZE 3 | ||
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static const u32 aux_offset[] = | ||
{ | ||
0x6200 - 0x6200, | ||
0x6250 - 0x6200, | ||
0x62a0 - 0x6200, | ||
0x6300 - 0x6200, | ||
0x6350 - 0x6200, | ||
0x63a0 - 0x6200, | ||
}; | ||
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ssize_t | ||
radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | ||
{ | ||
struct radeon_i2c_chan *chan = | ||
container_of(aux, struct radeon_i2c_chan, aux); | ||
struct drm_device *dev = chan->dev; | ||
struct radeon_device *rdev = dev->dev_private; | ||
int ret = 0, i; | ||
uint32_t tmp, ack = 0; | ||
int instance = chan->rec.i2c_id & 0xf; | ||
u8 byte; | ||
u8 *buf = msg->buffer; | ||
int retry_count = 0; | ||
int bytes; | ||
int msize; | ||
bool is_write = false; | ||
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if (WARN_ON(msg->size > 16)) | ||
return -E2BIG; | ||
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switch (msg->request & ~DP_AUX_I2C_MOT) { | ||
case DP_AUX_NATIVE_WRITE: | ||
case DP_AUX_I2C_WRITE: | ||
is_write = true; | ||
break; | ||
case DP_AUX_NATIVE_READ: | ||
case DP_AUX_I2C_READ: | ||
break; | ||
default: | ||
return -EINVAL; | ||
} | ||
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/* work out two sizes required */ | ||
msize = 0; | ||
bytes = BARE_ADDRESS_SIZE; | ||
if (msg->size) { | ||
msize = msg->size - 1; | ||
bytes++; | ||
if (is_write) | ||
bytes += msg->size; | ||
} | ||
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mutex_lock(&chan->mutex); | ||
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/* switch the pad to aux mode */ | ||
tmp = RREG32(chan->rec.mask_clk_reg); | ||
tmp |= (1 << 16); | ||
WREG32(chan->rec.mask_clk_reg, tmp); | ||
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/* setup AUX control register with correct HPD pin */ | ||
tmp = RREG32(AUX_CONTROL + aux_offset[instance]); | ||
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tmp &= AUX_HPD_SEL(0x7); | ||
tmp |= AUX_HPD_SEL(chan->rec.hpd); | ||
tmp |= AUX_EN | AUX_LS_READ_EN; | ||
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WREG32(AUX_CONTROL + aux_offset[instance], tmp); | ||
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/* atombios appears to write this twice lets copy it */ | ||
WREG32(AUX_SW_CONTROL + aux_offset[instance], | ||
AUX_SW_WR_BYTES(bytes)); | ||
WREG32(AUX_SW_CONTROL + aux_offset[instance], | ||
AUX_SW_WR_BYTES(bytes)); | ||
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/* write the data header into the registers */ | ||
/* request, addres, msg size */ | ||
byte = (msg->request << 4); | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); | ||
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byte = (msg->address >> 8) & 0xff; | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_MASK(byte)); | ||
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byte = msg->address & 0xff; | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_MASK(byte)); | ||
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byte = msize; | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_MASK(byte)); | ||
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/* if we are writing - write the msg buffer */ | ||
if (is_write) { | ||
for (i = 0; i < msg->size; i++) { | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_MASK(buf[i])); | ||
} | ||
} | ||
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/* clear the ACK */ | ||
WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); | ||
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/* write the size and GO bits */ | ||
WREG32(AUX_SW_CONTROL + aux_offset[instance], | ||
AUX_SW_WR_BYTES(bytes) | AUX_SW_GO); | ||
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/* poll the status registers - TODO irq support */ | ||
do { | ||
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]); | ||
if (tmp & AUX_SW_DONE) { | ||
break; | ||
} | ||
usleep_range(100, 200); | ||
} while (retry_count++ < 1000); | ||
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if (retry_count >= 1000) { | ||
DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp); | ||
ret = -EIO; | ||
goto done; | ||
} | ||
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if (tmp & AUX_SW_RX_TIMEOUT) { | ||
DRM_DEBUG_KMS("dp_aux_ch timed out\n"); | ||
ret = -ETIMEDOUT; | ||
goto done; | ||
} | ||
if (tmp & AUX_RX_ERROR_FLAGS) { | ||
DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp); | ||
ret = -EIO; | ||
goto done; | ||
} | ||
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bytes = AUX_SW_REPLY_GET_BYTE_COUNT(tmp); | ||
if (bytes) { | ||
WREG32(AUX_SW_DATA + aux_offset[instance], | ||
AUX_SW_DATA_RW | AUX_SW_AUTOINCREMENT_DISABLE); | ||
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tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); | ||
ack = (tmp >> 8) & 0xff; | ||
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for (i = 0; i < bytes - 1; i++) { | ||
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]); | ||
if (buf) | ||
buf[i] = (tmp >> 8) & 0xff; | ||
} | ||
if (buf) | ||
ret = bytes - 1; | ||
} | ||
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WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK); | ||
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if (is_write) | ||
ret = msg->size; | ||
done: | ||
mutex_unlock(&chan->mutex); | ||
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if (ret >= 0) | ||
msg->reply = ack >> 4; | ||
return ret; | ||
} |
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