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ARM: bcmring: use proper MMIO accessors
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A lot of code in bcmring just dereferences pointers to MMIO
locations, which is not safe. This annotates the pointers
correctly using __iomem and uses readl/write to access them.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann committed May 2, 2012
1 parent 8a3fb86 commit 878040e
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Showing 18 changed files with 306 additions and 304 deletions.
127 changes: 65 additions & 62 deletions arch/arm/mach-bcmring/csp/chipc/chipcHw.c
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80 changes: 35 additions & 45 deletions arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)

{
REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig2 =
chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET;
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET,
&pChipcHw->PLLConfig2);

pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
Expand All @@ -87,28 +87,30 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);

/* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);

/* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider2 = pllPreDivider2;
writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
/* Set NDIV Frac */
pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);

/* This has to be removed once the default values are fixed for PLL2. */
pChipcHw->PLLControl12 = 0x38000700;
pChipcHw->PLLControl22 = 0x00000015;
writel(0x38000700, &pChipcHw->PLLControl12);
writel(0x00000015, &pChipcHw->PLLControl22);

/* Reset PLL2 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
} else {
pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
chipcHw_REG_PLL_CONFIG_POWER_DOWN,
&pChipcHw->PLLConfig2);
}
REG_LOCAL_IRQ_RESTORE;
}
Expand All @@ -119,22 +121,25 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz)
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig2 &=
writel(readl(&pChipcHw->PLLConfig2) &
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
chipcHw_REG_PLL_CONFIG_POWER_DOWN),
&pChipcHw->PLLConfig2);

REG_LOCAL_IRQ_RESTORE;

}

/* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;

{
REG_LOCAL_IRQ_SAVE;
/* Remove digital reset */
pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
writel(readl(&pChipcHw->PLLConfig2) &
~chipcHw_REG_PLL_CONFIG_D_RESET,
&pChipcHw->PLLConfig2);

REG_LOCAL_IRQ_RESTORE;
}
Expand All @@ -157,9 +162,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{
REG_LOCAL_IRQ_SAVE;

pChipcHw->PLLConfig =
chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET;
writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET,
&pChipcHw->PLLConfig);
/* Setting VCO frequency */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pllPreDivider =
Expand All @@ -182,30 +187,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
}

/* Enable CHIPC registers to control the PLL */
pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);

/* Set pre divider to get desired VCO frequency */
pChipcHw->PLLPreDivider = pllPreDivider;
writel(pllPreDivider, &pChipcHw->PLLPreDivider);
/* Set NDIV Frac */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
} else {
pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
chipcHw_REG_PLL_DIVIDER_NDIV_f;
writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
}

/* Reset PLL1 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
} else {
pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
chipcHw_REG_PLL_CONFIG_POWER_DOWN;
writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
}

REG_LOCAL_IRQ_RESTORE;
Expand All @@ -216,22 +213,19 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
pChipcHw->PLLConfig &=
~(chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_POWER_DOWN);
writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}

/* Wait until PLL is locked */
while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
|| !(pChipcHw->
PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
|| !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;

/* Remove digital reset */
{
REG_LOCAL_IRQ_SAVE;
pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
}
Expand Down Expand Up @@ -267,11 +261,7 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);

/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
pChipcHw->ACLKClock =
(pChipcHw->
ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
armBusRatio &
chipcHw_REG_ACLKClock_CLK_DIV_MASK);
writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);

/* Set various core component frequencies. The order in which this is done is important for some. */
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
Expand Down
11 changes: 6 additions & 5 deletions arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
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Original file line number Diff line number Diff line change
Expand Up @@ -50,15 +50,16 @@ void chipcHw_reset(uint32_t mask)
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
/* Bypass the PLL clocks before reboot */
pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
&pChipcHw->UARTClock);
writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
&pChipcHw->SPIClock);

/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
do {
((uint32_t *) MM_IO_BASE_ARAM)[i] =
((uint32_t *) &chipcHw_reset_run_from_aram)[i];
writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
i++;
} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
} while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */

flush_cache_all();

Expand Down
21 changes: 10 additions & 11 deletions arch/arm/mach-bcmring/csp/dmac/dmacHw.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
/* ---- Include Files ---------------------------------------------------- */
#include <linux/types.h>
#include <linux/string.h>
#include <stddef.h>
#include <linux/stddef.h>

#include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h>
Expand Down Expand Up @@ -55,33 +55,32 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl
) {
uint32_t val = 0;
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
dmacHw_MISC_t *pMiscReg =
(dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);

switch (pCblk->channel) {
case 0:
val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
break;
case 1:
val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
break;
case 2:
val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
break;
case 3:
val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
break;
case 4:
val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
break;
case 5:
val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
break;
case 6:
val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
break;
case 7:
val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
break;
}

Expand Down
2 changes: 1 addition & 1 deletion arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,7 @@
/* ---- Include Files ---------------------------------------------------- */

#include <linux/types.h>
#include <stddef.h>
#include <linux/stddef.h>

#include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h>
Expand Down
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