Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 347371
b: refs/heads/master
c: 6e25e1b
h: refs/heads/master
i:
  347369: 7cd33db
  347367: 33f1156
v: v3
  • Loading branch information
Sivaram Nair authored and Stephen Warren committed Nov 26, 2012
1 parent 4a5c705 commit 88fd804
Show file tree
Hide file tree
Showing 2 changed files with 2 additions and 4 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 6eb583da959cf751eb951cc5ff488dd4e41f1b2f
refs/heads/master: 6e25e1b178ee3caf34f229bacfad5ae6780bcec6
4 changes: 1 addition & 3 deletions trunk/arch/arm/mach-tegra/tegra30_clocks.c
Original file line number Diff line number Diff line change
Expand Up @@ -1913,9 +1913,7 @@ struct clk_ops tegra30_periph_clk_ops = {
static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct clk *d = clk_get_sys(NULL, "pll_d");
/* The DSIB parent selection bit is in PLLD base
register - can not do direct r-m-w, must be
protected by PLLD lock */
/* The DSIB parent selection bit is in PLLD base register */
tegra_clk_cfg_ex(
d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);

Expand Down

0 comments on commit 88fd804

Please sign in to comment.