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r: 73331
b: refs/heads/master
c: 7f66c1f
h: refs/heads/master
i:
  73329: edde4af
  73327: 6606f5d
v: v3
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Grant Likely authored and Josh Boyer committed Nov 1, 2007
1 parent 916d343 commit 892275e
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2 changes: 1 addition & 1 deletion [refs]
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refs/heads/master: 2c84b4076c0cbbc44ffea2ae1da2a801fb23f081
refs/heads/master: 7f66c1fd03b64db5ddb24cc2ae150c9aebe30cb4
4 changes: 2 additions & 2 deletions trunk/Documentation/SubmittingPatches
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Expand Up @@ -464,8 +464,8 @@ section Linus Computer Science 101.
Nuff said. If your code deviates too much from this, it is likely
to be rejected without further review, and without comment.

One significant exception is when moving code from one file to
another -- in this case you should not modify the moved code at all in
Once significant exception is when moving code from one file to
another in this case you should not modify the moved code at all in
the same patch which moves it. This clearly delineates the act of
moving the code and your changes. This greatly aids review of the
actual differences and allows tools to better track the history of
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556 changes: 0 additions & 556 deletions trunk/Documentation/ja_JP/SubmittingPatches

This file was deleted.

14 changes: 2 additions & 12 deletions trunk/Documentation/powerpc/booting-without-of.txt
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Expand Up @@ -851,18 +851,12 @@ address which can extend beyond that limit.
/cpus/PowerPC,970FX@0
/cpus/PowerPC,970FX@1
(unit addresses do not require leading zeroes)
- d-cache-block-size : one cell, L1 data cache block size in bytes (*)
- i-cache-block-size : one cell, L1 instruction cache block size in
- d-cache-line-size : one cell, L1 data cache line size in bytes
- i-cache-line-size : one cell, L1 instruction cache line size in
bytes
- d-cache-size : one cell, size of L1 data cache in bytes
- i-cache-size : one cell, size of L1 instruction cache in bytes

(*) The cache "block" size is the size on which the cache management
instructions operate. Historically, this document used the cache
"line" size here which is incorrect. The kernel will prefer the cache
block size and will fallback to cache line size for backward
compatibility.

Recommended properties:

- timebase-frequency : a cell indicating the frequency of the
Expand All @@ -876,10 +870,6 @@ compatibility.
for the above, the common code doesn't use that property, but
you are welcome to re-use the pSeries or Maple one. A future
kernel version might provide a common function for this.
- d-cache-line-size : one cell, L1 data cache line size in bytes
if different from the block size
- i-cache-line-size : one cell, L1 instruction cache line size in
bytes if different from the block size

You are welcome to add any property you find relevant to your board,
like some information about the mechanism used to soft-reset the
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