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irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski
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Simon Horman
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Jun 18, 2013
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Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
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DT bindings for the R-/SH-Mobile irqpin controller | ||
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Required properties: | ||
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- compatible: has to be "renesas,intc-irqpin" | ||
- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in | ||
interrupts.txt in this directory | ||
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Optional properties: | ||
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- any properties, listed in interrupts.txt, and any standard resource allocation | ||
properties | ||
- sense-bitfield-width: width of a single sense bitfield in the SENSE register, | ||
if different from the default 4 bits |
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