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[ARM] omap: provide a NULL clock operations structure
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... and use it for clocks which are ALWAYS_ENABLED.  These clocks
use a non-NULL enable_reg pointer for other purposes (such as
selecting clock rates.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored and Russell King committed Feb 8, 2009
1 parent 548d849 commit 897dcde
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Showing 7 changed files with 135 additions and 93 deletions.
3 changes: 0 additions & 3 deletions arch/arm/mach-omap1/clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -515,9 +515,6 @@ static int omap1_clk_enable_generic(struct clk *clk)
__u16 regval16;
__u32 regval32;

if (clk->flags & ALWAYS_ENABLED)
return 0;

if (unlikely(clk->enable_reg == NULL)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
Expand Down
78 changes: 36 additions & 42 deletions arch/arm/mach-omap1/clock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -144,18 +144,18 @@ static struct mpu_rate rate_table[] = {

static struct clk ck_ref = {
.name = "ck_ref",
.ops = &clkops_generic,
.ops = &clkops_null,
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
CLOCK_IN_OMAP310,
};

static struct clk ck_dpll1 = {
.name = "ck_dpll1",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &ck_ref,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
CLOCK_IN_OMAP310 | RATE_PROPAGATES,
};

static struct arm_idlect1_clk ck_dpll1out = {
Expand Down Expand Up @@ -186,11 +186,10 @@ static struct clk sossi_ck = {

static struct clk arm_ck = {
.name = "arm_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
ALWAYS_ENABLED,
CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES,
.rate_offset = CKCTL_ARMDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
};
Expand Down Expand Up @@ -265,9 +264,9 @@ static struct arm_idlect1_clk armwdt_ck = {

static struct clk arminth_ck16xx = {
.name = "arminth_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &arm_ck,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc,
/* Note: On 16xx the frequency can be divided by 2 by programming
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
Expand All @@ -290,10 +289,10 @@ static struct clk dsp_ck = {

static struct clk dspmmu_ck = {
.name = "dspmmu_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
RATE_CKCTL | ALWAYS_ENABLED,
RATE_CKCTL,
.rate_offset = CKCTL_DSPMMUDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
};
Expand Down Expand Up @@ -337,12 +336,12 @@ static struct clk dsptim_ck = {
static struct arm_idlect1_clk tc_ck = {
.clk = {
.name = "tc_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &ck_dpll1,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
RATE_CKCTL | RATE_PROPAGATES |
ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
CLOCK_IDLE_CONTROL,
.rate_offset = CKCTL_TCDIV_OFFSET,
.recalc = &omap1_ckctl_recalc,
},
Expand All @@ -351,10 +350,9 @@ static struct arm_idlect1_clk tc_ck = {

static struct clk arminth_ck1510 = {
.name = "arminth_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
.recalc = &followparent_recalc,
/* Note: On 1510 the frequency follows TC_CK
*
Expand All @@ -365,10 +363,9 @@ static struct clk arminth_ck1510 = {
static struct clk tipb_ck = {
/* No-idle controlled by "tc_ck" */
.name = "tipb_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
.recalc = &followparent_recalc,
};

Expand Down Expand Up @@ -406,18 +403,18 @@ static struct clk tc2_ck = {
static struct clk dma_ck = {
/* No-idle controlled by "tc_ck" */
.name = "dma_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
CLOCK_IN_OMAP310,
.recalc = &followparent_recalc,
};

static struct clk dma_lcdfree_ck = {
.name = "dma_lcdfree_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc,
};

Expand Down Expand Up @@ -451,17 +448,17 @@ static struct arm_idlect1_clk lb_ck = {

static struct clk rhea1_ck = {
.name = "rhea1_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc,
};

static struct clk rhea2_ck = {
.name = "rhea2_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
.parent = &tc_ck.clk,
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
.flags = CLOCK_IN_OMAP16XX,
.recalc = &followparent_recalc,
};

Expand Down Expand Up @@ -493,13 +490,12 @@ static struct arm_idlect1_clk lcd_ck_1510 = {

static struct clk uart1_1510 = {
.name = "uart1_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = 29, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
Expand All @@ -523,13 +519,13 @@ static struct uart_clk uart1_16xx = {

static struct clk uart2_ck = {
.name = "uart2_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
CLOCK_NO_IDLE_PARENT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
Expand All @@ -538,13 +534,12 @@ static struct clk uart2_ck = {

static struct clk uart3_1510 = {
.name = "uart3_ck",
.ops = &clkops_generic,
.ops = &clkops_null,
/* Direct from ULPD, no real parent */
.parent = &armper_ck.clk,
.rate = 12000000,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
ENABLE_REG_32BIT | ALWAYS_ENABLED |
CLOCK_NO_IDLE_PARENT,
ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
.enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
.enable_bit = 31, /* Chooses between 12MHz and 48MHz */
.set_rate = &omap1_set_uart_rate,
Expand Down Expand Up @@ -680,9 +675,9 @@ static struct clk mmc2_ck = {

static struct clk virtual_ck_mpu = {
.name = "mpu",
.ops = &clkops_generic,
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
CLOCK_IN_OMAP310,
.parent = &arm_ck, /* Is smarter alias for */
.recalc = &followparent_recalc,
.set_rate = &omap1_select_table_rate,
Expand All @@ -694,19 +689,18 @@ remains active during MPU idle whenever this is enabled */
static struct clk i2c_fck = {
.name = "i2c_fck",
.id = 1,
.ops = &clkops_generic,
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
CLOCK_NO_IDLE_PARENT | ALWAYS_ENABLED,
CLOCK_NO_IDLE_PARENT,
.parent = &armxor_ck.clk,
.recalc = &followparent_recalc,
};

static struct clk i2c_ick = {
.name = "i2c_ick",
.id = 1,
.ops = &clkops_generic,
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
ALWAYS_ENABLED,
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT,
.parent = &armper_ck.clk,
.recalc = &followparent_recalc,
};
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/mach-omap2/clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -271,7 +271,7 @@ int _omap2_clk_enable(struct clk *clk)
{
u32 regval32;

if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
if (clk->flags & PARENT_CONTROLS_CLOCK)
return 0;

if (clk->ops && clk->ops->enable)
Expand Down Expand Up @@ -301,7 +301,7 @@ void _omap2_clk_disable(struct clk *clk)
{
u32 regval32;

if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
if (clk->flags & PARENT_CONTROLS_CLOCK)
return;

if (clk->ops && clk->ops->disable) {
Expand Down
31 changes: 22 additions & 9 deletions arch/arm/mach-omap2/clock24xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -619,9 +619,10 @@ static struct prcm_config rate_table[] = {
/* Base external input clocks */
static struct clk func_32k_ck = {
.name = "func_32k_ck",
.ops = &clkops_null,
.rate = 32000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate,
};
Expand All @@ -639,18 +640,20 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
/* Without modem likely 12MHz, with modem likely 13MHz */
static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
.name = "sys_ck", /* ~ ref_clk also */
.ops = &clkops_null,
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_sys_clk_recalc,
};

static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
.name = "alt_ck",
.ops = &clkops_null,
.rate = 54000000,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES,
RATE_FIXED | RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &propagate_rate,
};
Expand Down Expand Up @@ -679,10 +682,11 @@ static struct dpll_data dpll_dd = {
*/
static struct clk dpll_ck = {
.name = "dpll_ck",
.ops = &clkops_null,
.parent = &sys_ck, /* Can be func_32k also */
.dpll_data = &dpll_dd,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
RATE_PROPAGATES | ALWAYS_ENABLED,
RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &omap2_dpllcore_recalc,
.set_rate = &omap2_reprogram_dpllcore,
Expand Down Expand Up @@ -751,9 +755,10 @@ static struct clk func_54m_ck = {

static struct clk core_ck = {
.name = "core_ck",
.ops = &clkops_null,
.parent = &dpll_ck, /* can also be 32k */
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | RATE_PROPAGATES,
RATE_PROPAGATES,
.clkdm_name = "wkup_clkdm",
.recalc = &followparent_recalc,
};
Expand Down Expand Up @@ -837,6 +842,7 @@ static struct clk func_12m_ck = {
/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
.name = "ck_wdt1_osc",
.ops = &clkops_null, /* RMK: missing? */
.parent = &osc_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.recalc = &followparent_recalc,
Expand Down Expand Up @@ -996,9 +1002,10 @@ static const struct clksel mpu_clksel[] = {

static struct clk mpu_ck = { /* Control cpu */
.name = "mpu_ck",
.ops = &clkops_null,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "mpu_clkdm",
.init = &omap2_init_clksel_parent,
Expand Down Expand Up @@ -1168,9 +1175,10 @@ static const struct clksel core_l3_clksel[] = {

static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
.name = "core_l3_ck",
.ops = &clkops_null,
.parent = &core_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP |
DELAYED_APP |
CONFIG_PARTICIPANT | RATE_PROPAGATES,
.clkdm_name = "core_l3_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
Expand Down Expand Up @@ -1231,9 +1239,10 @@ static const struct clksel l4_clksel[] = {

static struct clk l4_ck = { /* used both as an ick and fck */
.name = "l4_ck",
.ops = &clkops_null,
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES,
DELAYED_APP | RATE_PROPAGATES,
.clkdm_name = "core_l4_clkdm",
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
.clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
Expand Down Expand Up @@ -2359,6 +2368,7 @@ static struct clk i2chs1_fck = {

static struct clk gpmc_fck = {
.name = "gpmc_fck",
.ops = &clkops_null, /* RMK: missing? */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ENABLE_ON_INIT,
Expand All @@ -2368,6 +2378,7 @@ static struct clk gpmc_fck = {

static struct clk sdma_fck = {
.name = "sdma_fck",
.ops = &clkops_null, /* RMK: missing? */
.parent = &core_l3_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
Expand All @@ -2376,6 +2387,7 @@ static struct clk sdma_fck = {

static struct clk sdma_ick = {
.name = "sdma_ick",
.ops = &clkops_null, /* RMK: missing? */
.parent = &l4_ck,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
.clkdm_name = "core_l3_clkdm",
Expand Down Expand Up @@ -2621,8 +2633,9 @@ static struct clk mmchsdb2_fck = {
*/
static struct clk virt_prcm_set = {
.name = "virt_prcm_set",
.ops = &clkops_null,
.flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
ALWAYS_ENABLED | DELAYED_APP,
DELAYED_APP,
.parent = &mpu_ck, /* Indexed by mpu speed, no parent */
.recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
.set_rate = &omap2_select_table_rate,
Expand Down
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