Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 281655
b: refs/heads/master
c: 0154867
h: refs/heads/master
i:
  281653: a0ebd8f
  281651: f523152
  281647: 6b14fba
v: v3
  • Loading branch information
Peter De Schrijver authored and Olof Johansson committed Dec 18, 2011
1 parent d2e62ad commit 8c035fd
Show file tree
Hide file tree
Showing 2 changed files with 11 additions and 6 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 9bfc3f0d48c0e6aac05b02638dd0b502b522dec7
refs/heads/master: 01548673fa15762137539d565767531eb4fef743
15 changes: 10 additions & 5 deletions trunk/arch/arm/mach-tegra/common.c
Original file line number Diff line number Diff line change
Expand Up @@ -75,15 +75,20 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
};
#endif

static void __init tegra_init_cache(void)
static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;

writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL);
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);

l2x0_init(p, 0x6C080001, 0x8200c3fe);
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x6C000001;

l2x0_init(p, aux_ctrl, 0x8200c3fe);
#endif

}
Expand All @@ -94,6 +99,6 @@ void __init tegra20_init_early(void)
tegra_init_fuse();
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache();
tegra_init_cache(0x331, 0x441);
}
#endif

0 comments on commit 8c035fd

Please sign in to comment.