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Staging: w35und: remove hw_data_t typedef
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As this typedef is used everywhere in the driver, remove it in a separate
patch.

Signed-off-by: Pekka Enberg <penberg@cs.helsinki.fi>
Acked-by: Pavel Machek <pavel@suse.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Pekka Enberg authored and Greg Kroah-Hartman committed Apr 3, 2009
1 parent eb62f3e commit 8e41b4b
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Showing 15 changed files with 196 additions and 197 deletions.
2 changes: 1 addition & 1 deletion drivers/staging/winbond/core.h
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ struct wbsoft_priv {
MLME_FRAME sMlmeFrame; // connect to peerSTA parameters

MTO_PARAMETERS sMtoPara; // MTO_struct ...
hw_data_t sHwData; //For HAL
struct hw_data sHwData; //For HAL
MDS Mds;

spinlock_t SpinLock;
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4 changes: 2 additions & 2 deletions drivers/staging/winbond/mds.c
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Original file line number Diff line number Diff line change
Expand Up @@ -418,7 +418,7 @@ static void Mds_HeaderCopy(struct wbsoft_priv * adapter, PDESCRIPTOR pDes, u8 *T
void
Mds_Tx(struct wbsoft_priv * adapter)
{
phw_data_t pHwData = &adapter->sHwData;
struct hw_data * pHwData = &adapter->sHwData;
PMDS pMds = &adapter->Mds;
DESCRIPTOR TxDes;
PDESCRIPTOR pTxDes = &TxDes;
Expand Down Expand Up @@ -561,7 +561,7 @@ void
Mds_SendComplete(struct wbsoft_priv * adapter, PT02_DESCRIPTOR pT02)
{
PMDS pMds = &adapter->Mds;
phw_data_t pHwData = &adapter->sHwData;
struct hw_data * pHwData = &adapter->sHwData;
u8 PacketId = (u8)pT02->T02_Tx_PktID;
unsigned char SendOK = true;
u8 RetryCount, TxRate;
Expand Down
26 changes: 13 additions & 13 deletions drivers/staging/winbond/phy_calibration.c
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Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,8 @@ static const fixed Angles[]=
};

/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
//void _phy_rf_write_delay(hw_data_t *phw_data);
//void phy_init_rf(hw_data_t *phw_data);
//void _phy_rf_write_delay(struct hw_data *phw_data);
//void phy_init_rf(struct hw_data *phw_data);

/****************** FUNCTION DEFINITION SECTION *****************************/

Expand Down Expand Up @@ -341,7 +341,7 @@ void _sin_cos(s32 angle, s32 *sin, s32 *cos)
}


void _reset_rx_cal(hw_data_t *phw_data)
void _reset_rx_cal(struct hw_data *phw_data)
{
u32 val;

Expand All @@ -366,7 +366,7 @@ void _reset_rx_cal(hw_data_t *phw_data)
//
//
// *********************************************
void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency)
void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
{
u32 reg_agc_ctrl3;
u32 reg_a_acq_ctrl;
Expand Down Expand Up @@ -465,7 +465,7 @@ void _rxadc_dc_offset_cancellation_winbond(hw_data_t *phw_data, u32 frequency)
}

////////////////////////////////////////////////////////
void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data)
void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
{
u32 reg_agc_ctrl3;
u32 reg_mode_ctrl;
Expand Down Expand Up @@ -600,7 +600,7 @@ void _txidac_dc_offset_cancellation_winbond(hw_data_t *phw_data)
}

///////////////////////////////////////////////////////
void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data)
void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
{
u32 reg_agc_ctrl3;
u32 reg_mode_ctrl;
Expand Down Expand Up @@ -726,7 +726,7 @@ void _txqdac_dc_offset_cacellation_winbond(hw_data_t *phw_data)
}

//20060612.1.a 20060718.1 Modify
u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data,
u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
s32 a_2_threshold,
s32 b_2_threshold)
{
Expand Down Expand Up @@ -1032,7 +1032,7 @@ u8 _tx_iq_calibration_loop_winbond(hw_data_t *phw_data,
return 1;
}

void _tx_iq_calibration_winbond(hw_data_t *phw_data)
void _tx_iq_calibration_winbond(struct hw_data *phw_data)
{
u32 reg_agc_ctrl3;
#ifdef _DEBUG
Expand Down Expand Up @@ -1195,7 +1195,7 @@ void _tx_iq_calibration_winbond(hw_data_t *phw_data)
}

/////////////////////////////////////////////////////////////////////////////////////////
u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequency)
u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
{
u32 reg_mode_ctrl;
s32 iqcal_tone_i;
Expand Down Expand Up @@ -1501,7 +1501,7 @@ u8 _rx_iq_calibration_loop_winbond(hw_data_t *phw_data, u16 factor, u32 frequenc
//////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////
void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency)
void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
{
// figo 20050523 marked thsi flag for can't compile for relesase
#ifdef _DEBUG
Expand Down Expand Up @@ -1579,7 +1579,7 @@ void _rx_iq_calibration_winbond(hw_data_t *phw_data, u32 frequency)
}

////////////////////////////////////////////////////////////////////////
void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency)
void phy_calibration_winbond(struct hw_data *phw_data, u32 frequency)
{
u32 reg_mode_ctrl;
u32 iq_alpha;
Expand Down Expand Up @@ -1618,7 +1618,7 @@ void phy_calibration_winbond(hw_data_t *phw_data, u32 frequency)
}

//===========================
void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value )
void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value )
{
u32 ltmp=0;

Expand Down Expand Up @@ -1660,7 +1660,7 @@ void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value )
}

// 20060717 modify as Bruce's mail
unsigned char adjust_TXVGA_for_iq_mag(hw_data_t *phw_data)
unsigned char adjust_TXVGA_for_iq_mag(struct hw_data *phw_data)
{
int init_txvga = 0;
u32 reg_mode_ctrl;
Expand Down
2 changes: 1 addition & 1 deletion drivers/staging/winbond/phy_calibration.h
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Original file line number Diff line number Diff line change
Expand Up @@ -101,7 +101,7 @@
//#define MASK_IQCAL_IMAGE_Q 0x03FFE000
//#define SHIFT_IQCAL_IMAGE_Q(x) ((x)>>13)

void phy_set_rf_data( phw_data_t pHwData, u32 index, u32 value );
void phy_set_rf_data( struct hw_data * pHwData, u32 index, u32 value );
#define phy_init_rf( _A ) //RFSynthesizer_initial( _A )

#endif
56 changes: 28 additions & 28 deletions drivers/staging/winbond/reg.c
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Original file line number Diff line number Diff line change
Expand Up @@ -915,7 +915,7 @@ u32 w89rf242_txvga_data[][5] =
// The address is stored in EthernetIDAddr.
//=============================================================================================================
void
Uxx_ReadEthernetAddress( phw_data_t pHwData )
Uxx_ReadEthernetAddress( struct hw_data * pHwData )
{
u32 ltmp;

Expand Down Expand Up @@ -964,7 +964,7 @@ void CardGetMulticastBit( u8 Address[ETH_ALEN], u8 *Byte, u8 *Value )
*Value = (u8) ((u8)1 << (BitNumber % 8));
}

void Uxx_power_on_procedure( phw_data_t pHwData )
void Uxx_power_on_procedure( struct hw_data * pHwData )
{
u32 ltmp, loop;

Expand Down Expand Up @@ -1008,7 +1008,7 @@ void Uxx_power_on_procedure( phw_data_t pHwData )
Wb35Reg_WriteSync( pHwData, 0x03f8, 0x7ff );
}

void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char number)
void Set_ChanIndep_RfData_al7230_24( struct hw_data * pHwData, u32 *pltmp ,char number)
{
u8 i;

Expand All @@ -1019,7 +1019,7 @@ void Set_ChanIndep_RfData_al7230_24( phw_data_t pHwData, u32 *pltmp ,char numbe
}
}

void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char number)
void Set_ChanIndep_RfData_al7230_50( struct hw_data * pHwData, u32 *pltmp, char number)
{
u8 i;

Expand All @@ -1035,7 +1035,7 @@ void Set_ChanIndep_RfData_al7230_50( phw_data_t pHwData, u32 *pltmp, char numbe
// RFSynthesizer_initial --
//=============================================================================================================
void
RFSynthesizer_initial(phw_data_t pHwData)
RFSynthesizer_initial(struct hw_data * pHwData)
{
u32 altmp[32];
u32 * pltmp = altmp;
Expand Down Expand Up @@ -1413,7 +1413,7 @@ RFSynthesizer_initial(phw_data_t pHwData)
}
}

void BBProcessor_AL7230_2400( phw_data_t pHwData)
void BBProcessor_AL7230_2400( struct hw_data * pHwData)
{
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[12];
Expand Down Expand Up @@ -1455,7 +1455,7 @@ void BBProcessor_AL7230_2400( phw_data_t pHwData)

}

void BBProcessor_AL7230_5000( phw_data_t pHwData)
void BBProcessor_AL7230_5000( struct hw_data * pHwData)
{
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[12];
Expand Down Expand Up @@ -1509,7 +1509,7 @@ void BBProcessor_AL7230_5000( phw_data_t pHwData)
// None.
//=============================================================================================================
void
BBProcessor_initial( phw_data_t pHwData )
BBProcessor_initial( struct hw_data * pHwData )
{
struct wb35_reg *reg = &pHwData->reg;
u32 i, pltmp[12];
Expand Down Expand Up @@ -1823,12 +1823,12 @@ BBProcessor_initial( phw_data_t pHwData )
reg->SQ3_filter[i] = 0x2f; // half of Bit 0 ~ 6
}

void set_tx_power_per_channel_max2829( phw_data_t pHwData, ChanInfo Channel)
void set_tx_power_per_channel_max2829( struct hw_data * pHwData, ChanInfo Channel)
{
RFSynthesizer_SetPowerIndex( pHwData, 100 ); // 20060620.1 Modify
}

void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
void set_tx_power_per_channel_al2230( struct hw_data * pHwData, ChanInfo Channel )
{
u8 index = 100;

Expand All @@ -1838,7 +1838,7 @@ void set_tx_power_per_channel_al2230( phw_data_t pHwData, ChanInfo Channel )
RFSynthesizer_SetPowerIndex( pHwData, index );
}

void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
void set_tx_power_per_channel_al7230( struct hw_data * pHwData, ChanInfo Channel)
{
u8 i, index = 100;

Expand Down Expand Up @@ -1868,7 +1868,7 @@ void set_tx_power_per_channel_al7230( phw_data_t pHwData, ChanInfo Channel)
RFSynthesizer_SetPowerIndex( pHwData, index );
}

void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
void set_tx_power_per_channel_wb242( struct hw_data * pHwData, ChanInfo Channel)
{
u8 index = 100;

Expand Down Expand Up @@ -1901,7 +1901,7 @@ void set_tx_power_per_channel_wb242( phw_data_t pHwData, ChanInfo Channel)
// None.
//=============================================================================================================
void
RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
RFSynthesizer_SwitchingChannel( struct hw_data * pHwData, ChanInfo Channel )
{
struct wb35_reg *reg = &pHwData->reg;
u32 pltmp[16]; // The 16 is the maximum capability of hardware
Expand Down Expand Up @@ -2129,7 +2129,7 @@ RFSynthesizer_SwitchingChannel( phw_data_t pHwData, ChanInfo Channel )
}

//Set the tx power directly from DUT GUI, not from the EEPROM. Return the current setting
u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
u8 RFSynthesizer_SetPowerIndex( struct hw_data * pHwData, u8 PowerIndex )
{
u32 Band = pHwData->band;
u8 index=0;
Expand Down Expand Up @@ -2187,7 +2187,7 @@ u8 RFSynthesizer_SetPowerIndex( phw_data_t pHwData, u8 PowerIndex )
}

//-- Sub function
u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetMaxim2828_24Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
if( index > 1 ) index = 1;
Expand All @@ -2196,7 +2196,7 @@ u8 RFSynthesizer_SetMaxim2828_24Power( phw_data_t pHwData, u8 index )
return index;
}
//--
u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetMaxim2828_50Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
if( index > 1 ) index = 1;
Expand All @@ -2205,7 +2205,7 @@ u8 RFSynthesizer_SetMaxim2828_50Power( phw_data_t pHwData, u8 index )
return index;
}
//--
u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetMaxim2827_24Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
if( index > 1 ) index = 1;
Expand All @@ -2214,7 +2214,7 @@ u8 RFSynthesizer_SetMaxim2827_24Power( phw_data_t pHwData, u8 index )
return index;
}
//--
u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetMaxim2827_50Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
if( index > 1 ) index = 1;
Expand All @@ -2223,7 +2223,7 @@ u8 RFSynthesizer_SetMaxim2827_50Power( phw_data_t pHwData, u8 index )
return index;
}
//--
u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetMaxim2825Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
if( index > 1 ) index = 1;
Expand All @@ -2232,7 +2232,7 @@ u8 RFSynthesizer_SetMaxim2825Power( phw_data_t pHwData, u8 index )
return index;
}
//--
u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetAiroha2230Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
u8 i,count;
Expand All @@ -2251,7 +2251,7 @@ u8 RFSynthesizer_SetAiroha2230Power( phw_data_t pHwData, u8 index )
return i;
}
//--
u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetAiroha7230Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
u8 i,count;
Expand All @@ -2270,7 +2270,7 @@ u8 RFSynthesizer_SetAiroha7230Power( phw_data_t pHwData, u8 index )
return i;
}

u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
u8 RFSynthesizer_SetWinbond242Power( struct hw_data * pHwData, u8 index )
{
u32 PowerData;
u8 i,count;
Expand Down Expand Up @@ -2311,7 +2311,7 @@ u8 RFSynthesizer_SetWinbond242Power( phw_data_t pHwData, u8 index )
// Initial the hardware setting and module variable
//
//===========================================================================================================
void Dxx_initial( phw_data_t pHwData )
void Dxx_initial( struct hw_data * pHwData )
{
struct wb35_reg *reg = &pHwData->reg;

Expand All @@ -2325,7 +2325,7 @@ void Dxx_initial( phw_data_t pHwData )
Wb35Reg_WriteSync( pHwData, 0x0400, reg->D00_DmaControl );
}

void Mxx_initial( phw_data_t pHwData )
void Mxx_initial( struct hw_data * pHwData )
{
struct wb35_reg *reg = &pHwData->reg;
u32 tmp;
Expand Down Expand Up @@ -2416,15 +2416,15 @@ void Mxx_initial( phw_data_t pHwData )
}


void Uxx_power_off_procedure( phw_data_t pHwData )
void Uxx_power_off_procedure( struct hw_data * pHwData )
{
// SW, PMU reset and turn off clock
Wb35Reg_WriteSync( pHwData, 0x03b0, 3 );
Wb35Reg_WriteSync( pHwData, 0x03f0, 0xf9 );
}

//Decide the TxVga of every channel
void GetTxVgaFromEEPROM( phw_data_t pHwData )
void GetTxVgaFromEEPROM( struct hw_data * pHwData )
{
u32 i, j, ltmp;
u16 Value[MAX_TXVGA_EEPROM];
Expand Down Expand Up @@ -2478,7 +2478,7 @@ void GetTxVgaFromEEPROM( phw_data_t pHwData )
// or RFSynthesizer_SetPowerIndex be called, new TxVga will take effect.
// TxVgaSettingInEEPROM of sHwData is an u8 array point to EEPROM contain for IS89C35
// This function will use default TxVgaSettingInEEPROM data to calculate new TxVga.
void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
void EEPROMTxVgaAdjust( struct hw_data * pHwData ) // 20060619.5 Add
{
u8 * pTxVga = pHwData->TxVgaSettingInEEPROM;
s16 i, stmp;
Expand Down Expand Up @@ -2618,7 +2618,7 @@ void EEPROMTxVgaAdjust( phw_data_t pHwData ) // 20060619.5 Add
#endif
}

void BBProcessor_RateChanging( phw_data_t pHwData, u8 rate ) // 20060613.1
void BBProcessor_RateChanging( struct hw_data * pHwData, u8 rate ) // 20060613.1
{
struct wb35_reg *reg = &pHwData->reg;
unsigned char Is11bRate;
Expand Down
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