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Merge tag 'renesas-boards-for-v3.10' of git://git.kernel.org/pub/scm/…
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From Simon Horman <horms+renesas@verge.net.au>:

Renesas ARM-based SoC board updates for v3.10

This is based on a merge of the following:

git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-for-v3.10

* tag 'renesas-boards-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (218 commits)
  ARM: shmobile: kzm9g: correct smsc regulator registration
  ARM: shmobile: marzen: Use gic_iid macro for ICCIAR / interrupt ID
  ARM: shmobile: kzm9g: Trim reference DT_MACHINE_START
  ARM: shmobile: kzm9g: Remove warning about SMP
  ARM: shmobile: simplify kzm9g Kconfig dependencies
  ARM: shmobile: SDHI and MMCIF interfaces to kzm9g-reference
  ARM: shmobile: parse DT and configure pinmux early on kzm9g-reference
  ARM: shmobile: kzm9g: Reference DT implementation
  ARM: shmobile: marzen: Reference DT implementation
  ARM: shmobile: mark mackerel sh_mmcif_device __maybe_unused
  ARM: shmobile: streamline mackerel SD and MMC devices
  ARM: shmobile: switch SDHI0 to GPIO regulator on armadillo800eva
  ARM: shmobile: use GPIO SD-card detection on armadillo800eva

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann committed Mar 21, 2013
2 parents f6161aa + 48296a1 commit 8f07b1d
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Showing 102 changed files with 10,745 additions and 6,083 deletions.
6 changes: 3 additions & 3 deletions Documentation/devicetree/bindings/gpio/gpio.txt
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;

}

Expand All @@ -107,8 +107,8 @@ where,

Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
by this gpio controller.
pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
pinctrl2 with gpio offset 10 is handled by this gpio controller.

The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node.
107 changes: 106 additions & 1 deletion Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
One-register-per-pin type device tree based pinctrl driver

Required properties:
- compatible : "pinctrl-single"
- compatible : "pinctrl-single" or "pinconf-single".
"pinctrl-single" means that pinconf isn't supported.
"pinconf-single" means that generic pinconf is supported.

- reg : offset and length of the register set for the mux registers

Expand All @@ -14,9 +16,61 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored

- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin

- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
current and drive strength mask.

/* drive strength current, mask */
pinctrl-single,power-source = <0x30 0xf0>;

- pinctrl-single,bias-pullup : array of value that are used to configure the
input bias pullup in the pinmux register.

/* input, enabled pullup bits, disabled pullup bits, mask */
pinctrl-single,bias-pullup = <0 1 0 1>;

- pinctrl-single,bias-pulldown : array of value that are used to configure the
input bias pulldown in the pinmux register.

/* input, enabled pulldown bits, disabled pulldown bits, mask */
pinctrl-single,bias-pulldown = <2 2 0 2>;

* Two bits to control input bias pullup and pulldown: User should use
pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
pullup, and the other one bit means pulldown.
* Three bits to control input bias enable, pullup and pulldown. User should
use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
enable bit should be included in pullup or pulldown bits.
* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
pinctrl-single,bias-disable. Because pinctrl single driver could implement
it by calling pulldown, pullup disabled.

- pinctrl-single,input-schmitt : array of value that are used to configure
input schmitt in the pinmux register. In some silicons, there're two input
schmitt value (rising-edge & falling-edge) in the pinmux register.

/* input schmitt value, mask */
pinctrl-single,input-schmitt = <0x30 0x70>;

- pinctrl-single,input-schmitt-enable : array of value that are used to
configure input schmitt enable or disable in the pinmux register.

/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;

- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
The number of parameters is depend on #pinctrl-single,gpio-range-cells
property.

/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;

This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
Expand All @@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.


Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.

Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
pinctrl-single,gpio-range property.

range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};


Example:

/* SoC common file */
Expand Down Expand Up @@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
pinctrl-single,function-mask = <0x5F>;
};

/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
compatible = "pinconf-single";
reg = <0xd401e000 0x0330>;
#address-cells = <1>;
#size-cells = <1>;
ranges;

pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;

/* sparse GPIO range could be supported */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;

range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};


/* board specific .dts file */

&pmx_core {
Expand All @@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
>;
};

uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 2>;
pinctrl-single,bias-pullup = <0 1 1>;
};

/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
Expand All @@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {

};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};

&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
Expand Down
2 changes: 2 additions & 0 deletions arch/arm/boot/dts/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -136,7 +136,9 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
r8a7779-marzen-reference.dtb \
sh73a0-kzm9g.dtb \
sh73a0-kzm9g-reference.dtb \
sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
socfpga_vt.dtb
Expand Down
47 changes: 47 additions & 0 deletions arch/arm/boot/dts/r8a7779-marzen-reference.dts
Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
/*
* Reference Device Tree Source for the Marzen board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/

/dts-v1/;
/include/ "r8a7779.dtsi"

/ {
model = "marzen";
compatible = "renesas,marzen-reference", "renesas,r8a7779";

chosen {
bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
};

memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};

fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};

lan0@18000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&gic>;
interrupts = <0 28 0x4>;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
};
98 changes: 98 additions & 0 deletions arch/arm/boot/dts/r8a7779.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,98 @@
/*
* Device Tree Source for Renesas r8a7779
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/

/include/ "skeleton.dtsi"

/ {
compatible = "renesas,r8a7779";

cpus {
#address-cells = <1>;
#size-cells = <0>;

cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
};
};

gic: interrupt-controller@f0001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xf0001000 0x1000>,
<0xf0000100 0x100>;
};

i2c0: i2c@0xffc70000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc70000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 79 0x4>;
};

i2c1: i2c@0xffc71000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc71000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 82 0x4>;
};

i2c2: i2c@0xffc72000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc72000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 80 0x4>;
};

i2c3: i2c@0xffc73000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc73000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 81 0x4>;
};

thermal@ffc48000 {
compatible = "renesas,rcar-thermal";
reg = <0xffc48000 0x38>;
};

sata: sata@fc600000 {
compatible = "renesas,rcar-sata";
reg = <0xfc600000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 100 0x4>;
};
};
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