---

yaml
---
r: 57819
b: refs/heads/master
c: d6fe89b
h: refs/heads/master
i:
  57817: 0f51b54
  57815: 24ad39b
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 27bb9e79bcfedc1888d23c3c212c189fa8534fe7
+refs/heads/master: d6fe89b0630080e2bd6ece20ff7b1b5c2647ed62

trunk/drivers/spi/spi_bfin5xx.c

@@ -582,14 +582,19 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 	dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
 	clear_dma_irqstat(CH_SPI);
 
+	/* Wait for DMA to complete */
+	while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
+		continue;
+
 	/*
-	 * wait for the last transaction shifted out.  yes, these two
-	 * while loops are supposed to be the same (see the HRM).
+	 * wait for the last transaction shifted out.  HRM states:
+	 * at this point there may still be data in the SPI DMA FIFO waiting
+	 * to be transmitted ... software needs to poll TXS in the SPI_STAT
+	 * register until it goes low for 2 successive reads
 	 */
 	if (drv_data->tx != NULL) {
-		while (bfin_read_SPI_STAT() & TXS)
-			continue;
-		while (bfin_read_SPI_STAT() & TXS)
+		while ((bfin_read_SPI_STAT() & TXS) ||
+		       (bfin_read_SPI_STAT() & TXS))
 			continue;
 	}