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V4L/DVB (7074): DiB7000P: correct tuning problem for 7MHz channel
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Tuning problem for 7Mhz channels fixes

Signed-off-by: Patrick Boettcher <pb@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
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Patrick Boettcher authored and Mauro Carvalho Chehab committed Jan 25, 2008
1 parent 3cb2c39 commit 904a82e
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Showing 2 changed files with 9 additions and 6 deletions.
10 changes: 4 additions & 6 deletions drivers/media/dvb/frontends/dib7000p.c
Original file line number Diff line number Diff line change
Expand Up @@ -35,8 +35,8 @@ struct dib7000p_state {

u16 wbd_ref;

u8 current_band;
fe_bandwidth_t current_bandwidth;
u8 current_band;
u32 current_bandwidth;
struct dibx000_agc_config *current_agc;
u32 timf;

Expand Down Expand Up @@ -1074,7 +1074,7 @@ static int dib7000p_get_frontend(struct dvb_frontend* fe,

fep->inversion = INVERSION_AUTO;

fep->u.ofdm.bandwidth = state->current_bandwidth;
fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);

switch ((tps >> 8) & 0x3) {
case 0: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K; break;
Expand Down Expand Up @@ -1131,10 +1131,8 @@ static int dib7000p_set_frontend(struct dvb_frontend* fe,
int time, ret;

dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
state->current_bandwidth = fep->u.ofdm.bandwidth;
dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->u.ofdm.bandwidth));

/* maybe the parameter has been changed */
/* maybe the parameter has been changed */
state->sfn_workaround_active = buggy_sfn_workaround;

if (fe->ops.tuner_ops.set_params)
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5 changes: 5 additions & 0 deletions drivers/media/dvb/frontends/dibx000_common.h
Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,11 @@ enum dibx000_adc_states {
(v) == BANDWIDTH_7_MHZ ? 7000 : \
(v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )

#define BANDWIDTH_TO_INDEX(v) ( \
(v) == 8000 ? BANDWIDTH_8_MHZ : \
(v) == 7000 ? BANDWIDTH_7_MHZ : \
(v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )

/* Chip output mode. */
#define OUTMODE_HIGH_Z 0
#define OUTMODE_MPEG2_PAR_GATED_CLK 1
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