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yaml --- r: 286870 b: refs/heads/master c: 14f991a h: refs/heads/master v: v3
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Jean-Christophe PLAGNIOL-VILLARD
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Nicolas Ferre
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Jan 20, 2012
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--- | ||
refs/heads/master: e9f68b5cc6160a473fc668054fd13f435fd4508b | ||
refs/heads/master: 14f991a730f453a1c8f114ccb686f83e158fdd92 |
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/* | ||
* reset AT91SAM9G45 as per errata | ||
* | ||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> | ||
* | ||
* unless the SDRAM is cleanly shutdown before we hit the | ||
* reset register it can be left driving the data bus and | ||
* killing the chance of a subsequent boot from NAND | ||
* | ||
* GPLv2 Only | ||
*/ | ||
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#include <linux/linkage.h> | ||
#include <mach/hardware.h> | ||
#include <mach/at91sam9_ddrsdr.h> | ||
#include <mach/at91_rstc.h> | ||
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.arm | ||
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.globl at91sam9g45_restart | ||
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at91sam9g45_restart: | ||
ldr r0, .at91_va_base_sdramc0 @ preload constants | ||
ldr r1, =at91_rstc_base | ||
ldr r1, [r1] | ||
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mov r2, #1 | ||
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN | ||
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST | ||
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.balign 32 @ align to cache line | ||
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str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access | ||
str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 | ||
str r4, [r1, #AT91_RSTC_CR] @ reset processor | ||
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b . | ||
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.at91_va_base_sdramc0: | ||
.word AT91_VA_BASE_SYS + AT91_DDRSDRC0 |
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