---

yaml
---
r: 48934
b: refs/heads/master
c: 07b0459
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4b210faf0944172e55489bef83babf520bccc1c4
+refs/heads/master: 07b04595e3630594773223874827f5bbd03fc289

trunk/arch/arm/plat-s3c24xx/sleep.S

@@ -64,11 +64,10 @@ ENTRY(s3c2410_cpu_save)
 
 	@@ store co-processor registers
 
-	mrc	p15, 0, r4, c15, c1, 0	@ CP access register
-	mrc	p15, 0, r5, c13, c0, 0	@ PID
-	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
-	mrc	p15, 0, r7, c2, c0, 0	@ translation table base address
-	mrc	p15, 0, r8, c1, c0, 0	@ control register
+	mrc	p15, 0, r4, c13, c0, 0	@ PID
+	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
+	mrc	p15, 0, r6, c2, c0, 0	@ translation table base address
+	mrc	p15, 0, r7, c1, c0, 0	@ control register
 
 	stmia	r0, { r4 - r13 }
 
@@ -141,18 +140,17 @@ ENTRY(s3c2410_cpu_resume)
 	ldr	r0, s3c2410_sleep_save_phys	@ address of restore block
 	ldmia	r0, { r4 - r13 }
 
-	mcr	p15, 0, r4, c15, c1, 0		@ CP access register
-	mcr	p15, 0, r5, c13, c0, 0		@ PID
-	mcr	p15, 0, r6, c3, c0, 0		@ Domain ID
-	mcr	p15, 0, r7, c2, c0, 0		@ translation table base
+	mcr	p15, 0, r4, c13, c0, 0		@ PID
+	mcr	p15, 0, r5, c3, c0, 0		@ Domain ID
+	mcr	p15, 0, r6, c2, c0, 0		@ translation table base
 
 #ifdef CONFIG_DEBUG_RESUME
 	mov	r3, #'R'
 	strb	r3, [ r2, #S3C2410_UTXH ]
 #endif
 
 	ldr	r2, =resume_with_mmu
-	mcr	p15, 0, r8, c1, c0, 0		@ turn on MMU, etc
+	mcr	p15, 0, r7, c1, c0, 0		@ turn on MMU, etc
 	nop					@ second-to-last before mmu
 	mov	pc, r2				@ go back to virtual address