---

yaml
---
r: 373940
b: refs/heads/master
c: fddddb5
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 02ac5b3fc5550e57b19a594e83efbb6af7bfa4fd
+refs/heads/master: fddddb52a6c4e2438f4514ed979183653ca0732a

trunk/arch/arm/mach-orion5x/pci.c

@@ -402,9 +402,8 @@ static void __init orion5x_pci_master_slave_enable(void)
 	orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 }
 
-static void __init orion5x_setup_pci_wins(void)
+static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
 {
-	const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
 	u32 win_enable;
 	int bus;
 	int i;
@@ -421,7 +420,7 @@ static void __init orion5x_setup_pci_wins(void)
 	bus = orion5x_pci_local_bus_nr();
 
 	for (i = 0; i < dram->num_cs; i++) {
-		const struct mbus_dram_window *cs = dram->cs + i;
+		struct mbus_dram_window *cs = dram->cs + i;
 		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
 		u32 reg;
 		u32 val;
@@ -468,7 +467,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
 	/*
 	 * Point PCI unit MBUS decode windows to DRAM space.
 	 */
-	orion5x_setup_pci_wins();
+	orion5x_setup_pci_wins(&orion_mbus_dram_info);
 
 	/*
 	 * Master + Slave enable

trunk/arch/arm/plat-orion/Makefile

@@ -3,11 +3,7 @@
 #
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-$(CONFIG_ARCH_MVEBU)          += addr-map.o
-obj-$(CONFIG_ARCH_KIRKWOOD)       += addr-map.o
-obj-$(CONFIG_ARCH_DOVE)           += addr-map.o
-obj-$(CONFIG_ARCH_ORION5X)        += addr-map.o
-obj-$(CONFIG_ARCH_MV78XX0)        += addr-map.o
+obj-y                             += addr-map.o
 
 orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o

trunk/arch/arm/plat-orion/gpio.c

@@ -439,64 +439,6 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 	}
 }
 
-#ifdef CONFIG_DEBUG_FS
-#include <linux/seq_file.h>
-
-static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
-	struct orion_gpio_chip *ochip =
-		container_of(chip, struct orion_gpio_chip, chip);
-	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
-	int i;
-
-	out	= readl_relaxed(GPIO_OUT(ochip));
-	io_conf	= readl_relaxed(GPIO_IO_CONF(ochip));
-	blink	= readl_relaxed(GPIO_BLINK_EN(ochip));
-	in_pol	= readl_relaxed(GPIO_IN_POL(ochip));
-	data_in	= readl_relaxed(GPIO_DATA_IN(ochip));
-	cause	= readl_relaxed(GPIO_EDGE_CAUSE(ochip));
-	edg_msk	= readl_relaxed(GPIO_EDGE_MASK(ochip));
-	lvl_msk	= readl_relaxed(GPIO_LEVEL_MASK(ochip));
-
-	for (i = 0; i < chip->ngpio; i++) {
-		const char *label;
-		u32 msk;
-		bool is_out;
-
-		label = gpiochip_is_requested(chip, i);
-		if (!label)
-			continue;
-
-		msk = 1 << i;
-		is_out = !(io_conf & msk);
-
-		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
-
-		if (is_out) {
-			seq_printf(s, " out %s %s\n",
-				   out & msk ? "hi" : "lo",
-				   blink & msk ? "(blink )" : "");
-			continue;
-		}
-
-		seq_printf(s, " in  %s (act %s) - IRQ",
-			   (data_in ^ in_pol) & msk  ? "hi" : "lo",
-			   in_pol & msk ? "lo" : "hi");
-		if (!((edg_msk | lvl_msk) & msk)) {
-			seq_printf(s, " disabled\n");
-			continue;
-		}
-		if (edg_msk & msk)
-			seq_printf(s, " edge ");
-		if (lvl_msk & msk)
-			seq_printf(s, " level");
-		seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
-	}
-}
-#else
-#define orion_gpio_dbg_show NULL
-#endif
-
 void __init orion_gpio_init(struct device_node *np,
 			    int gpio_base, int ngpio,
 			    void __iomem *base, int mask_offset,
@@ -529,7 +471,6 @@ void __init orion_gpio_init(struct device_node *np,
 #ifdef CONFIG_OF
 	ochip->chip.of_node = np;
 #endif
-	ochip->chip.dbg_show = orion_gpio_dbg_show;
 
 	spin_lock_init(&ochip->lock);
 	ochip->base = (void __iomem *)base;

trunk/arch/arm/plat-orion/pcie.c

@@ -120,14 +120,12 @@ void __init orion_pcie_reset(void __iomem *base)
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  * WIN[0-3] -> DRAM bank[0-3]
  */
-static void __init orion_pcie_setup_wins(void __iomem *base)
+static void __init orion_pcie_setup_wins(void __iomem *base,
+					 struct mbus_dram_target_info *dram)
 {
-	const struct mbus_dram_target_info *dram;
 	u32 size;
 	int i;
 
-	dram = mv_mbus_dram_info();
-
 	/*
 	 * First, disable and clear BARs and windows.
 	 */
@@ -152,7 +150,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base)
 	 */
 	size = 0;
 	for (i = 0; i < dram->num_cs; i++) {
-		const struct mbus_dram_window *cs = dram->cs + i;
+		struct mbus_dram_window *cs = dram->cs + i;
 
 		writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
 		writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -186,7 +184,7 @@ void __init orion_pcie_setup(void __iomem *base)
 	/*
 	 * Point PCIe unit MBUS decode windows to DRAM space.
 	 */
-	orion_pcie_setup_wins(base);
+	orion_pcie_setup_wins(base, &orion_mbus_dram_info);
 
 	/*
 	 * Master + slave enable.

trunk/drivers/bus/Kconfig

@@ -4,6 +4,13 @@
 
 menu "Bus devices"
 
+config MVEBU_MBUS
+	bool
+	depends on PLAT_ORION
+	help
+	  Driver needed for the MBus configuration on Marvell EBU SoCs
+	  (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP).
+
 config OMAP_OCP2SCP
 	tristate "OMAP OCP2SCP DRIVER"
 	depends on ARCH_OMAP2PLUS

trunk/drivers/bus/Makefile

@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.