Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 218812
b: refs/heads/master
c: ce2ca12
h: refs/heads/master
v: v3
  • Loading branch information
Rabin Vincent authored and Dan Williams committed Oct 19, 2010
1 parent 5deb251 commit 949049b
Show file tree
Hide file tree
Showing 23 changed files with 455 additions and 5,022 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 9cb047d4d19fc15791a64d900d483405eae6200d
refs/heads/master: ce2ca1252ba8688a4997b4104793540f4c28c0d8
8 changes: 6 additions & 2 deletions trunk/arch/arm/mach-imx/include/mach/dma-v1.h
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,6 @@

#define imx_has_dma_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())

#include <mach/dma.h>

#define IMX_DMA_CHANNELS 16

#define DMA_MODE_READ 0
Expand Down Expand Up @@ -98,6 +96,12 @@ int imx_dma_request(int channel, const char *name);

void imx_dma_free(int channel);

enum imx_dma_prio {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
};

int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);

#endif /* __MACH_DMA_V1_H__ */
67 changes: 0 additions & 67 deletions trunk/arch/arm/plat-mxc/include/mach/dma.h

This file was deleted.

17 changes: 0 additions & 17 deletions trunk/arch/arm/plat-mxc/include/mach/sdma.h

This file was deleted.

137 changes: 137 additions & 0 deletions trunk/arch/powerpc/include/asm/fsldma.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,137 @@
/*
* Freescale MPC83XX / MPC85XX DMA Controller
*
* Copyright (c) 2009 Ira W. Snyder <iws@ovro.caltech.edu>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/

#ifndef __ARCH_POWERPC_ASM_FSLDMA_H__
#define __ARCH_POWERPC_ASM_FSLDMA_H__

#include <linux/slab.h>
#include <linux/dmaengine.h>

/*
* Definitions for the Freescale DMA controller's DMA_SLAVE implemention
*
* The Freescale DMA_SLAVE implementation was designed to handle many-to-many
* transfers. An example usage would be an accelerated copy between two
* scatterlists. Another example use would be an accelerated copy from
* multiple non-contiguous device buffers into a single scatterlist.
*
* A DMA_SLAVE transaction is defined by a struct fsl_dma_slave. This
* structure contains a list of hardware addresses that should be copied
* to/from the scatterlist passed into device_prep_slave_sg(). The structure
* also has some fields to enable hardware-specific features.
*/

/**
* struct fsl_dma_hw_addr
* @entry: linked list entry
* @address: the hardware address
* @length: length to transfer
*
* Holds a single physical hardware address / length pair for use
* with the DMAEngine DMA_SLAVE API.
*/
struct fsl_dma_hw_addr {
struct list_head entry;

dma_addr_t address;
size_t length;
};

/**
* struct fsl_dma_slave
* @addresses: a linked list of struct fsl_dma_hw_addr structures
* @request_count: value for DMA request count
* @src_loop_size: setup and enable constant source-address DMA transfers
* @dst_loop_size: setup and enable constant destination address DMA transfers
* @external_start: enable externally started DMA transfers
* @external_pause: enable externally paused DMA transfers
*
* Holds a list of address / length pairs for use with the DMAEngine
* DMA_SLAVE API implementation for the Freescale DMA controller.
*/
struct fsl_dma_slave {

/* List of hardware address/length pairs */
struct list_head addresses;

/* Support for extra controller features */
unsigned int request_count;
unsigned int src_loop_size;
unsigned int dst_loop_size;
bool external_start;
bool external_pause;
};

/**
* fsl_dma_slave_append - add an address/length pair to a struct fsl_dma_slave
* @slave: the &struct fsl_dma_slave to add to
* @address: the hardware address to add
* @length: the length of bytes to transfer from @address
*
* Add a hardware address/length pair to a struct fsl_dma_slave. Returns 0 on
* success, -ERRNO otherwise.
*/
static inline int fsl_dma_slave_append(struct fsl_dma_slave *slave,
dma_addr_t address, size_t length)
{
struct fsl_dma_hw_addr *addr;

addr = kzalloc(sizeof(*addr), GFP_ATOMIC);
if (!addr)
return -ENOMEM;

INIT_LIST_HEAD(&addr->entry);
addr->address = address;
addr->length = length;

list_add_tail(&addr->entry, &slave->addresses);
return 0;
}

/**
* fsl_dma_slave_free - free a struct fsl_dma_slave
* @slave: the struct fsl_dma_slave to free
*
* Free a struct fsl_dma_slave and all associated address/length pairs
*/
static inline void fsl_dma_slave_free(struct fsl_dma_slave *slave)
{
struct fsl_dma_hw_addr *addr, *tmp;

if (slave) {
list_for_each_entry_safe(addr, tmp, &slave->addresses, entry) {
list_del(&addr->entry);
kfree(addr);
}

kfree(slave);
}
}

/**
* fsl_dma_slave_alloc - allocate a struct fsl_dma_slave
* @gfp: the flags to pass to kmalloc when allocating this structure
*
* Allocate a struct fsl_dma_slave for use by the DMA_SLAVE API. Returns a new
* struct fsl_dma_slave on success, or NULL on failure.
*/
static inline struct fsl_dma_slave *fsl_dma_slave_alloc(gfp_t gfp)
{
struct fsl_dma_slave *slave;

slave = kzalloc(sizeof(*slave), gfp);
if (!slave)
return NULL;

INIT_LIST_HEAD(&slave->addresses);
return slave;
}

#endif /* __ARCH_POWERPC_ASM_FSLDMA_H__ */
13 changes: 13 additions & 0 deletions trunk/crypto/async_tx/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,19 @@ config ASYNC_RAID6_RECOV
select ASYNC_PQ
select ASYNC_XOR

config ASYNC_RAID6_TEST
tristate "Self test for hardware accelerated raid6 recovery"
depends on ASYNC_RAID6_RECOV
select ASYNC_MEMCPY
---help---
This is a one-shot self test that permutes through the
recovery of all the possible two disk failure scenarios for a
N-disk array. Recovery is performed with the asynchronous
raid6 recovery routines, and will optionally use an offload
engine if one is available.

If unsure, say N.

config ASYNC_TX_DISABLE_PQ_VAL_DMA
bool

Expand Down
31 changes: 2 additions & 29 deletions trunk/drivers/dma/Kconfig
Original file line number Diff line number Diff line change
Expand Up @@ -46,22 +46,15 @@ config INTEL_MID_DMAC

If unsure, say N.

config ASYNC_TX_ENABLE_CHANNEL_SWITCH
config ASYNC_TX_DISABLE_CHANNEL_SWITCH
bool

config AMBA_PL08X
bool "ARM PrimeCell PL080 or PL081 support"
depends on ARM_AMBA && EXPERIMENTAL
select DMA_ENGINE
help
Platform has a PL08x DMAC device
which can provide DMA engine support

config INTEL_IOATDMA
tristate "Intel I/OAT DMA support"
depends on PCI && X86
select DMA_ENGINE
select DCA
select ASYNC_TX_DISABLE_CHANNEL_SWITCH
select ASYNC_TX_DISABLE_PQ_VAL_DMA
select ASYNC_TX_DISABLE_XOR_VAL_DMA
help
Expand All @@ -76,7 +69,6 @@ config INTEL_IOP_ADMA
tristate "Intel IOP ADMA support"
depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX
select DMA_ENGINE
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
help
Enable support for the Intel(R) IOP Series RAID engines.

Expand All @@ -101,7 +93,6 @@ config FSL_DMA
tristate "Freescale Elo and Elo Plus DMA support"
depends on FSL_SOC
select DMA_ENGINE
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
---help---
Enable support for the Freescale Elo and Elo Plus DMA controllers.
The Elo is the DMA controller on some 82xx and 83xx parts, and the
Expand All @@ -118,7 +109,6 @@ config MV_XOR
bool "Marvell XOR engine support"
depends on PLAT_ORION
select DMA_ENGINE
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
---help---
Enable support for the Marvell XOR engine.

Expand Down Expand Up @@ -176,7 +166,6 @@ config AMCC_PPC440SPE_ADMA
depends on 440SPe || 440SP
select DMA_ENGINE
select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
select ASYNC_TX_ENABLE_CHANNEL_SWITCH
help
Enable support for the AMCC PPC440SPe RAID engines.

Expand Down Expand Up @@ -206,22 +195,6 @@ config PCH_DMA
help
Enable support for the Topcliff PCH DMA engine.

config IMX_SDMA
tristate "i.MX SDMA support"
depends on ARCH_MX25 || ARCH_MX3 || ARCH_MX5
select DMA_ENGINE
help
Support the i.MX SDMA engine. This engine is integrated into
Freescale i.MX25/31/35/51 chips.

config IMX_DMA
tristate "i.MX DMA support"
depends on ARCH_MX1 || ARCH_MX21 || MACH_MX27
select DMA_ENGINE
help
Support the i.MX DMA engine. This engine is integrated into
Freescale i.MX1/21/27 chips.

config DMA_ENGINE
bool

Expand Down
3 changes: 0 additions & 3 deletions trunk/drivers/dma/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,7 @@ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
obj-$(CONFIG_SH_DMAE) += shdma.o
obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
obj-$(CONFIG_IMX_SDMA) += imx-sdma.o
obj-$(CONFIG_IMX_DMA) += imx-dma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
obj-$(CONFIG_PL330_DMA) += pl330.o
obj-$(CONFIG_PCH_DMA) += pch_dma.o
obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
Loading

0 comments on commit 949049b

Please sign in to comment.