Skip to content

Commit

Permalink
[SCSI] lpfc 8.3.37: Provide support for FCoE protocol dual-chute (ULP…
Browse files Browse the repository at this point in the history 
…) operation

Signed-off-by: James Smart <james.smart@emulex.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
  • Loading branch information
James Smart authored and James Bottomley committed Jan 30, 2013
1 parent 8b455cf commit 962bc51
Show file tree
Hide file tree
Showing 5 changed files with 369 additions and 84 deletions.
9 changes: 9 additions & 0 deletions drivers/scsi/lpfc/lpfc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -752,6 +752,15 @@ struct lpfc_hba {
void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
PCI BAR2 */

void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
PCI BAR0 with dual-ULP support */
void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
PCI BAR2 with dual-ULP support */
void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
PCI BAR4 with dual-ULP support */
#define PCI_64BIT_BAR0 0
#define PCI_64BIT_BAR2 2
#define PCI_64BIT_BAR4 4
void __iomem *MBslimaddr; /* virtual address for mbox cmds */
void __iomem *HAregaddr; /* virtual address for host attn reg */
void __iomem *CAregaddr; /* virtual address for chip attn reg */
Expand Down
176 changes: 107 additions & 69 deletions drivers/scsi/lpfc/lpfc_hw4.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,7 @@ struct lpfc_sli_intf {

#define LPFC_SLI4_MB_WORD_COUNT 64
#define LPFC_MAX_MQ_PAGE 8
#define LPFC_MAX_WQ_PAGE_V0 4
#define LPFC_MAX_WQ_PAGE 8
#define LPFC_MAX_CQ_PAGE 4
#define LPFC_MAX_EQ_PAGE 8
Expand Down Expand Up @@ -703,24 +704,41 @@ struct lpfc_register {
* BAR0. The offsets are the same so the driver must account for
* any base address difference.
*/
#define LPFC_RQ_DOORBELL 0x00A0
#define lpfc_rq_doorbell_num_posted_SHIFT 16
#define lpfc_rq_doorbell_num_posted_MASK 0x3FFF
#define lpfc_rq_doorbell_num_posted_WORD word0
#define lpfc_rq_doorbell_id_SHIFT 0
#define lpfc_rq_doorbell_id_MASK 0xFFFF
#define lpfc_rq_doorbell_id_WORD word0

#define LPFC_WQ_DOORBELL 0x0040
#define lpfc_wq_doorbell_num_posted_SHIFT 24
#define lpfc_wq_doorbell_num_posted_MASK 0x00FF
#define lpfc_wq_doorbell_num_posted_WORD word0
#define lpfc_wq_doorbell_index_SHIFT 16
#define lpfc_wq_doorbell_index_MASK 0x00FF
#define lpfc_wq_doorbell_index_WORD word0
#define lpfc_wq_doorbell_id_SHIFT 0
#define lpfc_wq_doorbell_id_MASK 0xFFFF
#define lpfc_wq_doorbell_id_WORD word0
#define LPFC_ULP0_RQ_DOORBELL 0x00A0
#define LPFC_ULP1_RQ_DOORBELL 0x00C0
#define lpfc_rq_db_list_fm_num_posted_SHIFT 24
#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
#define lpfc_rq_db_list_fm_num_posted_WORD word0
#define lpfc_rq_db_list_fm_index_SHIFT 16
#define lpfc_rq_db_list_fm_index_MASK 0x00FF
#define lpfc_rq_db_list_fm_index_WORD word0
#define lpfc_rq_db_list_fm_id_SHIFT 0
#define lpfc_rq_db_list_fm_id_MASK 0xFFFF
#define lpfc_rq_db_list_fm_id_WORD word0
#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
#define lpfc_rq_db_ring_fm_num_posted_WORD word0
#define lpfc_rq_db_ring_fm_id_SHIFT 0
#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
#define lpfc_rq_db_ring_fm_id_WORD word0

#define LPFC_ULP0_WQ_DOORBELL 0x0040
#define LPFC_ULP1_WQ_DOORBELL 0x0060
#define lpfc_wq_db_list_fm_num_posted_SHIFT 24
#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
#define lpfc_wq_db_list_fm_num_posted_WORD word0
#define lpfc_wq_db_list_fm_index_SHIFT 16
#define lpfc_wq_db_list_fm_index_MASK 0x00FF
#define lpfc_wq_db_list_fm_index_WORD word0
#define lpfc_wq_db_list_fm_id_SHIFT 0
#define lpfc_wq_db_list_fm_id_MASK 0xFFFF
#define lpfc_wq_db_list_fm_id_WORD word0
#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
#define lpfc_wq_db_ring_fm_num_posted_WORD word0
#define lpfc_wq_db_ring_fm_id_SHIFT 0
#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
#define lpfc_wq_db_ring_fm_id_WORD word0

#define LPFC_EQCQ_DOORBELL 0x0120
#define lpfc_eqcq_doorbell_se_SHIFT 31
Expand Down Expand Up @@ -1131,12 +1149,22 @@ struct lpfc_mbx_wq_create {
struct { /* Version 0 Request */
uint32_t word0;
#define lpfc_mbx_wq_create_num_pages_SHIFT 0
#define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF
#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
#define lpfc_mbx_wq_create_num_pages_WORD word0
#define lpfc_mbx_wq_create_dua_SHIFT 8
#define lpfc_mbx_wq_create_dua_MASK 0x00000001
#define lpfc_mbx_wq_create_dua_WORD word0
#define lpfc_mbx_wq_create_cq_id_SHIFT 16
#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
#define lpfc_mbx_wq_create_cq_id_WORD word0
struct dma_address page[LPFC_MAX_WQ_PAGE];
struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
uint32_t word9;
#define lpfc_mbx_wq_create_bua_SHIFT 0
#define lpfc_mbx_wq_create_bua_MASK 0x00000001
#define lpfc_mbx_wq_create_bua_WORD word9
#define lpfc_mbx_wq_create_ulp_num_SHIFT 8
#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
#define lpfc_mbx_wq_create_ulp_num_WORD word9
} request;
struct { /* Version 1 Request */
uint32_t word0; /* Word 0 is the same as in v0 */
Expand All @@ -1160,6 +1188,17 @@ struct lpfc_mbx_wq_create {
#define lpfc_mbx_wq_create_q_id_SHIFT 0
#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
#define lpfc_mbx_wq_create_q_id_WORD word0
uint32_t doorbell_offset;
uint32_t word2;
#define lpfc_mbx_wq_create_bar_set_SHIFT 0
#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
#define lpfc_mbx_wq_create_bar_set_WORD word2
#define WQ_PCI_BAR_0_AND_1 0x00
#define WQ_PCI_BAR_2_AND_3 0x01
#define WQ_PCI_BAR_4_AND_5 0x02
#define lpfc_mbx_wq_create_db_format_SHIFT 16
#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
#define lpfc_mbx_wq_create_db_format_WORD word2
} response;
} u;
};
Expand Down Expand Up @@ -1223,14 +1262,31 @@ struct lpfc_mbx_rq_create {
#define lpfc_mbx_rq_create_num_pages_SHIFT 0
#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
#define lpfc_mbx_rq_create_num_pages_WORD word0
#define lpfc_mbx_rq_create_dua_SHIFT 16
#define lpfc_mbx_rq_create_dua_MASK 0x00000001
#define lpfc_mbx_rq_create_dua_WORD word0
#define lpfc_mbx_rq_create_bqu_SHIFT 17
#define lpfc_mbx_rq_create_bqu_MASK 0x00000001
#define lpfc_mbx_rq_create_bqu_WORD word0
#define lpfc_mbx_rq_create_ulp_num_SHIFT 24
#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
#define lpfc_mbx_rq_create_ulp_num_WORD word0
struct rq_context context;
struct dma_address page[LPFC_MAX_WQ_PAGE];
} request;
struct {
uint32_t word0;
#define lpfc_mbx_rq_create_q_id_SHIFT 0
#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
#define lpfc_mbx_rq_create_q_id_WORD word0
#define lpfc_mbx_rq_create_q_id_SHIFT 0
#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
#define lpfc_mbx_rq_create_q_id_WORD word0
uint32_t doorbell_offset;
uint32_t word2;
#define lpfc_mbx_rq_create_bar_set_SHIFT 0
#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
#define lpfc_mbx_rq_create_bar_set_WORD word2
#define lpfc_mbx_rq_create_db_format_SHIFT 16
#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
#define lpfc_mbx_rq_create_db_format_WORD word2
} response;
} u;
};
Expand Down Expand Up @@ -1388,6 +1444,33 @@ struct lpfc_mbx_get_rsrc_extent_info {
} u;
};

struct lpfc_mbx_query_fw_config {
struct mbox_header header;
struct {
uint32_t config_number;
#define LPFC_FC_FCOE 0x00000007
uint32_t asic_revision;
uint32_t physical_port;
uint32_t function_mode;
#define LPFC_FCOE_INI_MODE 0x00000040
#define LPFC_FCOE_TGT_MODE 0x00000080
#define LPFC_DUA_MODE 0x00000800
uint32_t ulp0_mode;
#define LPFC_ULP_FCOE_INIT_MODE 0x00000040
#define LPFC_ULP_FCOE_TGT_MODE 0x00000080
uint32_t ulp0_nap_words[12];
uint32_t ulp1_mode;
uint32_t ulp1_nap_words[12];
uint32_t function_capabilities;
uint32_t cqid_base;
uint32_t cqid_tot;
uint32_t eqid_base;
uint32_t eqid_tot;
uint32_t ulp0_nap2_words[2];
uint32_t ulp1_nap2_words[2];
} rsp;
};

struct lpfc_id_range {
uint32_t word5;
#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
Expand Down Expand Up @@ -1803,51 +1886,6 @@ struct lpfc_mbx_redisc_fcf_tbl {
#define lpfc_mbx_redisc_fcf_index_WORD word12
};

struct lpfc_mbx_query_fw_cfg {
struct mbox_header header;
uint32_t config_number;
uint32_t asic_rev;
uint32_t phys_port;
uint32_t function_mode;
/* firmware Function Mode */
#define lpfc_function_mode_toe_SHIFT 0
#define lpfc_function_mode_toe_MASK 0x00000001
#define lpfc_function_mode_toe_WORD function_mode
#define lpfc_function_mode_nic_SHIFT 1
#define lpfc_function_mode_nic_MASK 0x00000001
#define lpfc_function_mode_nic_WORD function_mode
#define lpfc_function_mode_rdma_SHIFT 2
#define lpfc_function_mode_rdma_MASK 0x00000001
#define lpfc_function_mode_rdma_WORD function_mode
#define lpfc_function_mode_vm_SHIFT 3
#define lpfc_function_mode_vm_MASK 0x00000001
#define lpfc_function_mode_vm_WORD function_mode
#define lpfc_function_mode_iscsi_i_SHIFT 4
#define lpfc_function_mode_iscsi_i_MASK 0x00000001
#define lpfc_function_mode_iscsi_i_WORD function_mode
#define lpfc_function_mode_iscsi_t_SHIFT 5
#define lpfc_function_mode_iscsi_t_MASK 0x00000001
#define lpfc_function_mode_iscsi_t_WORD function_mode
#define lpfc_function_mode_fcoe_i_SHIFT 6
#define lpfc_function_mode_fcoe_i_MASK 0x00000001
#define lpfc_function_mode_fcoe_i_WORD function_mode
#define lpfc_function_mode_fcoe_t_SHIFT 7
#define lpfc_function_mode_fcoe_t_MASK 0x00000001
#define lpfc_function_mode_fcoe_t_WORD function_mode
#define lpfc_function_mode_dal_SHIFT 8
#define lpfc_function_mode_dal_MASK 0x00000001
#define lpfc_function_mode_dal_WORD function_mode
#define lpfc_function_mode_lro_SHIFT 9
#define lpfc_function_mode_lro_MASK 0x00000001
#define lpfc_function_mode_lro_WORD function_mode
#define lpfc_function_mode_flex10_SHIFT 10
#define lpfc_function_mode_flex10_MASK 0x00000001
#define lpfc_function_mode_flex10_WORD function_mode
#define lpfc_function_mode_ncsi_SHIFT 11
#define lpfc_function_mode_ncsi_MASK 0x00000001
#define lpfc_function_mode_ncsi_WORD function_mode
};

/* Status field for embedded SLI_CONFIG mailbox command */
#define STATUS_SUCCESS 0x0
#define STATUS_FAILED 0x1
Expand Down Expand Up @@ -2965,7 +3003,7 @@ struct lpfc_mqe {
struct lpfc_mbx_read_config rd_config;
struct lpfc_mbx_request_features req_ftrs;
struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
struct lpfc_mbx_query_fw_cfg query_fw_cfg;
struct lpfc_mbx_query_fw_config query_fw_cfg;
struct lpfc_mbx_supp_pages supp_pages;
struct lpfc_mbx_pc_sli4_params sli4_params;
struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
Expand Down
72 changes: 68 additions & 4 deletions drivers/scsi/lpfc/lpfc_init.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6233,9 +6233,11 @@ lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
phba->sli4_hba.conf_regs_memmap_p +
LPFC_CTL_PORT_SEM_OFFSET;
phba->sli4_hba.RQDBregaddr =
phba->sli4_hba.conf_regs_memmap_p + LPFC_RQ_DOORBELL;
phba->sli4_hba.conf_regs_memmap_p +
LPFC_ULP0_RQ_DOORBELL;
phba->sli4_hba.WQDBregaddr =
phba->sli4_hba.conf_regs_memmap_p + LPFC_WQ_DOORBELL;
phba->sli4_hba.conf_regs_memmap_p +
LPFC_ULP0_WQ_DOORBELL;
phba->sli4_hba.EQCQDBregaddr =
phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
phba->sli4_hba.MQDBregaddr =
Expand Down Expand Up @@ -6289,9 +6291,11 @@ lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
return -ENODEV;

phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
vf * LPFC_VFR_PAGE_SIZE + LPFC_RQ_DOORBELL);
vf * LPFC_VFR_PAGE_SIZE +
LPFC_ULP0_RQ_DOORBELL);
phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
vf * LPFC_VFR_PAGE_SIZE + LPFC_WQ_DOORBELL);
vf * LPFC_VFR_PAGE_SIZE +
LPFC_ULP0_WQ_DOORBELL);
phba->sli4_hba.EQCQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
vf * LPFC_VFR_PAGE_SIZE + LPFC_EQCQ_DOORBELL);
phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
Expand Down Expand Up @@ -6987,6 +6991,19 @@ lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
phba->sli4_hba.fcp_wq = NULL;
}

if (phba->pci_bar0_memmap_p) {
iounmap(phba->pci_bar0_memmap_p);
phba->pci_bar0_memmap_p = NULL;
}
if (phba->pci_bar2_memmap_p) {
iounmap(phba->pci_bar2_memmap_p);
phba->pci_bar2_memmap_p = NULL;
}
if (phba->pci_bar4_memmap_p) {
iounmap(phba->pci_bar4_memmap_p);
phba->pci_bar4_memmap_p = NULL;
}

/* Release FCP CQ mapping array */
if (phba->sli4_hba.fcp_cq_map != NULL) {
kfree(phba->sli4_hba.fcp_cq_map);
Expand Down Expand Up @@ -7050,6 +7067,53 @@ lpfc_sli4_queue_setup(struct lpfc_hba *phba)
int rc = -ENOMEM;
int fcp_eqidx, fcp_cqidx, fcp_wqidx;
int fcp_cq_index = 0;
uint32_t shdr_status, shdr_add_status;
union lpfc_sli4_cfg_shdr *shdr;
LPFC_MBOXQ_t *mboxq;
uint32_t length;

/* Check for dual-ULP support */
mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
if (!mboxq) {
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"3249 Unable to allocate memory for "
"QUERY_FW_CFG mailbox command\n");
return -ENOMEM;
}
length = (sizeof(struct lpfc_mbx_query_fw_config) -
sizeof(struct lpfc_sli4_cfg_mhdr));
lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
LPFC_MBOX_OPCODE_QUERY_FW_CFG,
length, LPFC_SLI4_MBX_EMBED);

rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);

shdr = (union lpfc_sli4_cfg_shdr *)
&mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
if (shdr_status || shdr_add_status || rc) {
lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
"3250 QUERY_FW_CFG mailbox failed with status "
"x%x add_status x%x, mbx status x%x\n",
shdr_status, shdr_add_status, rc);
if (rc != MBX_TIMEOUT)
mempool_free(mboxq, phba->mbox_mem_pool);
rc = -ENXIO;
goto out_error;
}

phba->sli4_hba.fw_func_mode =
mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
"3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
"ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);

if (rc != MBX_TIMEOUT)
mempool_free(mboxq, phba->mbox_mem_pool);

/*
* Set up HBA Event Queues (EQs)
Expand Down
Loading

0 comments on commit 962bc51

Please sign in to comment.