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r: 183475
b: refs/heads/master
c: bf3af54
h: refs/heads/master
i:
  183473: 7a2a710
  183471: 7a2c6b0
v: v3
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Wolfgang Grandegger authored and David S. Miller committed Jan 8, 2010
1 parent 8b14c3b commit 966c2ec
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Showing 5 changed files with 296 additions and 96 deletions.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 2d4b6faf7d1818e9a52ae9f068ab4ffd9c3be923
refs/heads/master: bf3af54732bea5894ccc2cbde3ab566f0af7da56
7 changes: 4 additions & 3 deletions trunk/drivers/net/can/mscan/Kconfig
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Expand Up @@ -11,12 +11,13 @@ if CAN_MSCAN

config CAN_MPC5XXX
tristate "Freescale MPC5xxx onboard CAN controller"
depends on PPC_MPC52xx
depends on (PPC_MPC52xx || PPC_MPC512x)
---help---
If you say yes here you get support for Freescale's MPC5xxx
onboard CAN controller.
onboard CAN controller. Currently, the MPC5200, MPC5200B and
MPC5121 (Rev. 2 and later) are supported.

This driver can also be built as a module. If so, the module
This driver can also be built as a module. If so, the module
will be called mscan-mpc5xxx.ko.

endif
Expand Down
246 changes: 204 additions & 42 deletions trunk/drivers/net/can/mscan/mpc5xxx_can.c
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Original file line number Diff line number Diff line change
Expand Up @@ -29,29 +29,29 @@
#include <linux/can/dev.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/mpc52xx.h>

#include "mscan.h"

#define DRV_NAME "mpc5xxx_can"

static struct of_device_id mpc52xx_cdm_ids[] __devinitdata = {
struct mpc5xxx_can_data {
unsigned int type;
u32 (*get_clock)(struct of_device *ofdev, const char *clock_name,
int *mscan_clksrc);
};

#ifdef CONFIG_PPC_MPC5200
static struct of_device_id __devinitdata mpc52xx_cdm_ids[] = {
{ .compatible = "fsl,mpc5200-cdm", },
{}
};

/*
* Get frequency of the MSCAN clock source
*
* Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock (IP_CLK)
* can be selected. According to the MPC5200 user's manual, the oscillator
* clock is the better choice as it has less jitter but due to a hardware
* bug, it can not be selected for the old MPC5200 Rev. A chips.
*/

static unsigned int __devinit mpc52xx_can_clock_freq(struct of_device *of,
int clock_src)
static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev,
const char *clock_name,
int *mscan_clksrc)
{
unsigned int pvr;
struct mpc52xx_cdm __iomem *cdm;
Expand All @@ -61,11 +61,24 @@ static unsigned int __devinit mpc52xx_can_clock_freq(struct of_device *of,

pvr = mfspr(SPRN_PVR);

freq = mpc5xxx_get_bus_frequency(of->node);
/*
* Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
* (IP_CLK) can be selected as MSCAN clock source. According to
* the MPC5200 user's manual, the oscillator clock is the better
* choice as it has less jitter. For this reason, it is selected
* by default. Unfortunately, it can not be selected for the old
* MPC5200 Rev. A chips due to a hardware bug (check errata).
*/
if (clock_name && strcmp(clock_name, "ip") == 0)
*mscan_clksrc = MSCAN_CLKSRC_BUS;
else
*mscan_clksrc = MSCAN_CLKSRC_XTAL;

freq = mpc5xxx_get_bus_frequency(ofdev->node);
if (!freq)
return 0;

if (clock_src == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
return freq;

/* Determine SYS_XTAL_IN frequency from the clock domain settings */
Expand All @@ -75,7 +88,6 @@ static unsigned int __devinit mpc52xx_can_clock_freq(struct of_device *of,
return 0;
}
cdm = of_iomap(np_cdm, 0);
of_node_put(np_cdm);

if (in_8(&cdm->ipb_clk_sel) & 0x1)
freq *= 2;
Expand All @@ -84,26 +96,174 @@ static unsigned int __devinit mpc52xx_can_clock_freq(struct of_device *of,
freq *= (val & (1 << 5)) ? 8 : 4;
freq /= (val & (1 << 6)) ? 12 : 16;

of_node_put(np_cdm);
iounmap(cdm);

return freq;
}
#else /* !CONFIG_PPC_MPC5200 */
static u32 __devinit mpc52xx_can_get_clock(struct of_device *ofdev,
const char *clock_name,
int *mscan_clksrc)
{
return 0;
}
#endif /* CONFIG_PPC_MPC5200 */

#ifdef CONFIG_PPC_MPC512x
struct mpc512x_clockctl {
u32 spmr; /* System PLL Mode Reg */
u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
u32 scfr1; /* System Clk Freq Reg 1 */
u32 scfr2; /* System Clk Freq Reg 2 */
u32 reserved;
u32 bcr; /* Bread Crumb Reg */
u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
u32 spccr; /* SPDIF Clk Ctrl Reg */
u32 cccr; /* CFM Clk Ctrl Reg */
u32 dccr; /* DIU Clk Cnfg Reg */
u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
};

static struct of_device_id __devinitdata mpc512x_clock_ids[] = {
{ .compatible = "fsl,mpc5121-clock", },
{}
};

static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev,
const char *clock_name,
int *mscan_clksrc)
{
struct mpc512x_clockctl __iomem *clockctl;
struct device_node *np_clock;
struct clk *sys_clk, *ref_clk;
int plen, clockidx, clocksrc = -1;
u32 sys_freq, val, clockdiv = 1, freq = 0;
const u32 *pval;

np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
if (!np_clock) {
dev_err(&ofdev->dev, "couldn't find clock node\n");
return -ENODEV;
}
clockctl = of_iomap(np_clock, 0);
if (!clockctl) {
dev_err(&ofdev->dev, "couldn't map clock registers\n");
return 0;
}

/* Determine the MSCAN device index from the physical address */
pval = of_get_property(ofdev->node, "reg", &plen);
BUG_ON(!pval || plen < sizeof(*pval));
clockidx = (*pval & 0x80) ? 1 : 0;
if (*pval & 0x2000)
clockidx += 2;

/*
* Clock source and divider selection: 3 different clock sources
* can be selected: "ip", "ref" or "sys". For the latter two, a
* clock divider can be defined as well. If the clock source is
* not specified by the device tree, we first try to find an
* optimal CAN source clock based on the system clock. If that
* is not posslible, the reference clock will be used.
*/
if (clock_name && !strcmp(clock_name, "ip")) {
*mscan_clksrc = MSCAN_CLKSRC_IPS;
freq = mpc5xxx_get_bus_frequency(ofdev->node);
} else {
*mscan_clksrc = MSCAN_CLKSRC_BUS;

pval = of_get_property(ofdev->node,
"fsl,mscan-clock-divider", &plen);
if (pval && plen == sizeof(*pval))
clockdiv = *pval;
if (!clockdiv)
clockdiv = 1;

if (!clock_name || !strcmp(clock_name, "sys")) {
sys_clk = clk_get(&ofdev->dev, "sys_clk");
if (!sys_clk) {
dev_err(&ofdev->dev, "couldn't get sys_clk\n");
goto exit_unmap;
}
/* Get and round up/down sys clock rate */
sys_freq = 1000000 *
((clk_get_rate(sys_clk) + 499999) / 1000000);

if (!clock_name) {
/* A multiple of 16 MHz would be optimal */
if ((sys_freq % 16000000) == 0) {
clocksrc = 0;
clockdiv = sys_freq / 16000000;
freq = sys_freq / clockdiv;
}
} else {
clocksrc = 0;
freq = sys_freq / clockdiv;
}
}

if (clocksrc < 0) {
ref_clk = clk_get(&ofdev->dev, "ref_clk");
if (!ref_clk) {
dev_err(&ofdev->dev, "couldn't get ref_clk\n");
goto exit_unmap;
}
clocksrc = 1;
freq = clk_get_rate(ref_clk) / clockdiv;
}
}

/* Disable clock */
out_be32(&clockctl->mccr[clockidx], 0x0);
if (clocksrc >= 0) {
/* Set source and divider */
val = (clocksrc << 14) | ((clockdiv - 1) << 17);
out_be32(&clockctl->mccr[clockidx], val);
/* Enable clock */
out_be32(&clockctl->mccr[clockidx], val | 0x10000);
}

/* Enable MSCAN clock domain */
val = in_be32(&clockctl->sccr[1]);
if (!(val & (1 << 25)))
out_be32(&clockctl->sccr[1], val | (1 << 25));

dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
*mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);

exit_unmap:
of_node_put(np_clock);
iounmap(clockctl);

return freq;
}
#else /* !CONFIG_PPC_MPC512x */
static u32 __devinit mpc512x_can_get_clock(struct of_device *ofdev,
const char *clock_name,
int *mscan_clksrc)
{
return 0;
}
#endif /* CONFIG_PPC_MPC512x */

static int __devinit mpc5xxx_can_probe(struct of_device *ofdev,
const struct of_device_id *id)
{
struct mpc5xxx_can_data *data = (struct mpc5xxx_can_data *)id->data;
struct device_node *np = ofdev->node;
struct net_device *dev;
struct mscan_priv *priv;
void __iomem *base;
const char *clk_src;
int err, irq, clock_src;
const char *clock_name = NULL;
int irq, mscan_clksrc = 0;
int err = -ENOMEM;

base = of_iomap(ofdev->node, 0);
base = of_iomap(np, 0);
if (!base) {
dev_err(&ofdev->dev, "couldn't ioremap\n");
err = -ENOMEM;
goto exit_release_mem;
return err;
}

irq = irq_of_parse_and_map(np, 0);
Expand All @@ -114,37 +274,27 @@ static int __devinit mpc5xxx_can_probe(struct of_device *ofdev,
}

dev = alloc_mscandev();
if (!dev) {
err = -ENOMEM;
if (!dev)
goto exit_dispose_irq;
}

priv = netdev_priv(dev);
priv->reg_base = base;
dev->irq = irq;

/*
* Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
* (IP_CLK) can be selected as MSCAN clock source. According to
* the MPC5200 user's manual, the oscillator clock is the better
* choice as it has less jitter. For this reason, it is selected
* by default.
*/
clk_src = of_get_property(np, "fsl,mscan-clock-source", NULL);
if (clk_src && strcmp(clk_src, "ip") == 0)
clock_src = MSCAN_CLKSRC_BUS;
else
clock_src = MSCAN_CLKSRC_XTAL;
priv->can.clock.freq = mpc52xx_can_clock_freq(ofdev, clock_src);
clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);

BUG_ON(!data);
priv->type = data->type;
priv->can.clock.freq = data->get_clock(ofdev, clock_name,
&mscan_clksrc);
if (!priv->can.clock.freq) {
dev_err(&ofdev->dev, "couldn't get MSCAN clock frequency\n");
err = -ENODEV;
dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
goto exit_free_mscan;
}

SET_NETDEV_DEV(dev, &ofdev->dev);

err = register_mscandev(dev, clock_src);
err = register_mscandev(dev, mscan_clksrc);
if (err) {
dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
DRV_NAME, err);
Expand All @@ -164,7 +314,7 @@ static int __devinit mpc5xxx_can_probe(struct of_device *ofdev,
irq_dispose_mapping(irq);
exit_unmap_mem:
iounmap(base);
exit_release_mem:

return err;
}

Expand Down Expand Up @@ -225,8 +375,20 @@ static int mpc5xxx_can_resume(struct of_device *ofdev)
}
#endif

static struct mpc5xxx_can_data __devinitdata mpc5200_can_data = {
.type = MSCAN_TYPE_MPC5200,
.get_clock = mpc52xx_can_get_clock,
};

static struct mpc5xxx_can_data __devinitdata mpc5121_can_data = {
.type = MSCAN_TYPE_MPC5121,
.get_clock = mpc512x_can_get_clock,
};

static struct of_device_id __devinitdata mpc5xxx_can_table[] = {
{.compatible = "fsl,mpc5200-mscan"},
{ .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
/* Note that only MPC5121 Rev. 2 (and later) is supported */
{ .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
{},
};

Expand Down Expand Up @@ -255,5 +417,5 @@ static void __exit mpc5xxx_can_exit(void)
module_exit(mpc5xxx_can_exit);

MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
MODULE_DESCRIPTION("Freescale MPC5200 CAN driver");
MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
MODULE_LICENSE("GPL v2");
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