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Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-soc
* 'next/soc' of git://git.linaro.org/people/arnd/arm-soc: (21 commits) MAINTAINERS: add ARM/FREESCALE IMX6 entry arm/imx: merge i.MX3 and i.MX6 arm/imx6q: add suspend/resume support arm/imx6q: add device tree machine support arm/imx6q: add smp and cpu hotplug support arm/imx6q: add core drivers clock, gpc, mmdc and src arm/imx: add gic_handle_irq function arm/imx6q: add core definitions and low-level debug uart arm/imx6q: add device tree source ARM: highbank: add suspend support ARM: highbank: Add cpu hotplug support ARM: highbank: add SMP support MAINTAINERS: add Calxeda Highbank ARM platform ARM: add Highbank core platform support ARM: highbank: add devicetree source ARM: l2x0: add empty l2x0_of_init picoxcell: add a definition of VMALLOC_END picoxcell: remove custom ioremap implementation picoxcell: add the DTS for the PC7302 board picoxcell: add the DTS for pc3x2 and pc3x3 devices ... Fix up trivial conflicts in arch/arm/Kconfig, and some more header file conflicts in arch/arm/mach-omap2/board-generic.c (as per an ealier merge by Arnd).
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,8 @@ | ||
| Calxeda Highbank Platforms Device Tree Bindings | ||
| ----------------------------------------------- | ||
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| Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following | ||
| properties. | ||
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| Required root node properties: | ||
| - compatible = "calxeda,highbank"; |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,24 @@ | ||
| Picochip picoXcell device tree bindings. | ||
| ======================================== | ||
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| Required root node properties: | ||
| - compatible: | ||
| - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. | ||
| - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. | ||
| - "picochip,pc3x3" : picoXcell PC3X3 device based board. | ||
| - "picochip,pc3x2" : picoXcell PC3X2 device based board. | ||
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| Timers required properties: | ||
| - compatible = "picochip,pc3x2-timer" | ||
| - interrupts : The single IRQ line for the timer. | ||
| - clock-freq : The frequency in HZ of the timer. | ||
| - reg : The register bank for the timer. | ||
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| Note: two timers are required - one for the scheduler clock and one for the | ||
| event tick/NOHZ. | ||
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| VIC required properties: | ||
| - compatible = "arm,pl192-vic". | ||
| - interrupt-controller. | ||
| - reg : The register bank for the device. | ||
| - #interrupt-cells : Must be 1. |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,198 @@ | ||
| /* | ||
| * Copyright 2011 Calxeda, Inc. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify it | ||
| * under the terms and conditions of the GNU General Public License, | ||
| * version 2, as published by the Free Software Foundation. | ||
| * | ||
| * This program is distributed in the hope it will be useful, but WITHOUT | ||
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| * more details. | ||
| * | ||
| * You should have received a copy of the GNU General Public License along with | ||
| * this program. If not, see <http://www.gnu.org/licenses/>. | ||
| */ | ||
|
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| /dts-v1/; | ||
|
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| /* First 4KB has pen for secondary cores. */ | ||
| /memreserve/ 0x00000000 0x0001000; | ||
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| / { | ||
| model = "Calxeda Highbank"; | ||
| compatible = "calxeda,highbank"; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
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| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| cpu@0 { | ||
| compatible = "arm,cortex-a9"; | ||
| reg = <0>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
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| cpu@1 { | ||
| compatible = "arm,cortex-a9"; | ||
| reg = <1>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
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| cpu@2 { | ||
| compatible = "arm,cortex-a9"; | ||
| reg = <2>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
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| cpu@3 { | ||
| compatible = "arm,cortex-a9"; | ||
| reg = <3>; | ||
| next-level-cache = <&L2>; | ||
| }; | ||
| }; | ||
|
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| memory { | ||
| name = "memory"; | ||
| device_type = "memory"; | ||
| reg = <0x00000000 0xff900000>; | ||
| }; | ||
|
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| chosen { | ||
| bootargs = "console=ttyAMA0"; | ||
| }; | ||
|
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| soc { | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| compatible = "simple-bus"; | ||
| interrupt-parent = <&intc>; | ||
| ranges; | ||
|
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| timer@fff10600 { | ||
| compatible = "arm,smp-twd"; | ||
| reg = <0xfff10600 0x20>; | ||
| interrupts = <1 13 0xf04>; | ||
| }; | ||
|
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| watchdog@fff10620 { | ||
| compatible = "arm,cortex-a9-wdt"; | ||
| reg = <0xfff10620 0x20>; | ||
| interrupts = <1 14 0xf04>; | ||
| }; | ||
|
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| intc: interrupt-controller@fff11000 { | ||
| compatible = "arm,cortex-a9-gic"; | ||
| #interrupt-cells = <3>; | ||
| #size-cells = <0>; | ||
| #address-cells = <1>; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| reg = <0xfff11000 0x1000>, | ||
| <0xfff10100 0x100>; | ||
| }; | ||
|
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| L2: l2-cache { | ||
| compatible = "arm,pl310-cache"; | ||
| reg = <0xfff12000 0x1000>; | ||
| interrupts = <0 70 4>; | ||
| cache-unified; | ||
| cache-level = <2>; | ||
| }; | ||
|
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| pmu { | ||
| compatible = "arm,cortex-a9-pmu"; | ||
| interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; | ||
| }; | ||
|
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| sata@ffe08000 { | ||
| compatible = "calxeda,hb-ahci"; | ||
| reg = <0xffe08000 0x10000>; | ||
| interrupts = <0 83 4>; | ||
| }; | ||
|
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| sdhci@ffe0e000 { | ||
| compatible = "calxeda,hb-sdhci"; | ||
| reg = <0xffe0e000 0x1000>; | ||
| interrupts = <0 90 4>; | ||
| }; | ||
|
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| ipc@fff20000 { | ||
| compatible = "arm,pl320", "arm,primecell"; | ||
| reg = <0xfff20000 0x1000>; | ||
| interrupts = <0 7 4>; | ||
| }; | ||
|
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| gpioe: gpio@fff30000 { | ||
| #gpio-cells = <2>; | ||
| compatible = "arm,pl061", "arm,primecell"; | ||
| gpio-controller; | ||
| reg = <0xfff30000 0x1000>; | ||
| interrupts = <0 14 4>; | ||
| }; | ||
|
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| gpiof: gpio@fff31000 { | ||
| #gpio-cells = <2>; | ||
| compatible = "arm,pl061", "arm,primecell"; | ||
| gpio-controller; | ||
| reg = <0xfff31000 0x1000>; | ||
| interrupts = <0 15 4>; | ||
| }; | ||
|
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| gpiog: gpio@fff32000 { | ||
| #gpio-cells = <2>; | ||
| compatible = "arm,pl061", "arm,primecell"; | ||
| gpio-controller; | ||
| reg = <0xfff32000 0x1000>; | ||
| interrupts = <0 16 4>; | ||
| }; | ||
|
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| gpioh: gpio@fff33000 { | ||
| #gpio-cells = <2>; | ||
| compatible = "arm,pl061", "arm,primecell"; | ||
| gpio-controller; | ||
| reg = <0xfff33000 0x1000>; | ||
| interrupts = <0 17 4>; | ||
| }; | ||
|
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| timer { | ||
| compatible = "arm,sp804", "arm,primecell"; | ||
| reg = <0xfff34000 0x1000>; | ||
| interrupts = <0 18 4>; | ||
| }; | ||
|
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| rtc@fff35000 { | ||
| compatible = "arm,pl031", "arm,primecell"; | ||
| reg = <0xfff35000 0x1000>; | ||
| interrupts = <0 19 4>; | ||
| }; | ||
|
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| serial@fff36000 { | ||
| compatible = "arm,pl011", "arm,primecell"; | ||
| reg = <0xfff36000 0x1000>; | ||
| interrupts = <0 20 4>; | ||
| }; | ||
|
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| smic@fff3a000 { | ||
| compatible = "ipmi-smic"; | ||
| device_type = "ipmi"; | ||
| reg = <0xfff3a000 0x1000>; | ||
| interrupts = <0 24 4>; | ||
| reg-size = <4>; | ||
| reg-spacing = <4>; | ||
| }; | ||
|
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| sregs@fff3c000 { | ||
| compatible = "calxeda,hb-sregs"; | ||
| reg = <0xfff3c000 0x1000>; | ||
| }; | ||
|
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| dma@fff3d000 { | ||
| compatible = "arm,pl330", "arm,primecell"; | ||
| reg = <0xfff3d000 0x1000>; | ||
| interrupts = <0 92 4>; | ||
| }; | ||
| }; | ||
| }; |
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