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[ARM] S3C64XX: GPIO definitions for BANKS A,B,C
GPIO register and configuration definitions for GPIO banks A, B and C. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
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Ben Dooks
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Dec 15, 2008
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| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank A register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) | ||
| #define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) | ||
| #define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) | ||
| #define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) | ||
| #define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) | ||
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| #define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| #define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| #define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
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| #define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) | ||
| #define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) | ||
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| #define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) | ||
| #define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) | ||
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| #define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) | ||
| #define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) | ||
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| #define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) | ||
| #define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) | ||
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| #define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) | ||
| #define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) | ||
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| #define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) | ||
| #define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) | ||
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| #define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) | ||
| #define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) | ||
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| #define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) | ||
| #define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) | ||
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| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank B register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) | ||
| #define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) | ||
| #define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) | ||
| #define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) | ||
| #define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) | ||
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| #define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| #define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| #define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
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| #define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) | ||
| #define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) | ||
| #define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) | ||
| #define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) | ||
| #define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) | ||
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| #define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) | ||
| #define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) | ||
| #define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) | ||
| #define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) | ||
| #define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) | ||
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| #define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) | ||
| #define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) | ||
| #define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) | ||
| #define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) | ||
| #define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) | ||
| #define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) | ||
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| #define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) | ||
| #define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) | ||
| #define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) | ||
| #define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) | ||
| #define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) | ||
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| #define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) | ||
| #define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) | ||
| #define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) | ||
| #define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) | ||
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| #define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) | ||
| #define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) | ||
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| #define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) | ||
| #define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,53 @@ | ||
| /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h | ||
| * | ||
| * Copyright 2008 Openmoko, Inc. | ||
| * Copyright 2008 Simtec Electronics | ||
| * Ben Dooks <ben@simtec.co.uk> | ||
| * http://armlinux.simtec.co.uk/ | ||
| * | ||
| * GPIO Bank C register and configuration definitions | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) | ||
| #define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) | ||
| #define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) | ||
| #define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) | ||
| #define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) | ||
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| #define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| #define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| #define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
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| #define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) | ||
| #define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) | ||
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| #define S3C64XX_GPC1_SPI_CLKO (0x02 << 4) | ||
| #define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) | ||
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| #define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8) | ||
| #define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) | ||
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| #define S3C64XX_GPC3_SPI_nCSO (0x02 << 12) | ||
| #define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) | ||
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| #define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) | ||
| #define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) | ||
| #define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) | ||
| #define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) | ||
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| #define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) | ||
| #define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) | ||
| #define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) | ||
| #define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) | ||
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| #define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) | ||
| #define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) | ||
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| #define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) | ||
| #define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) | ||
| #define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) | ||
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