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yaml
---
r: 308415
b: refs/heads/master
c: eeed66e
h: refs/heads/master
i:
  308413: d7abdb0
  308411: f8cfdef
  308407: 09d7e96
  308399: 81bc81e
  308383: 5c9a907
  308351: 55f3a38
v: v3
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Changhwan Youn authored and Kukjin Kim committed May 15, 2012
1 parent 63c0c59 commit 9a0ebec
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Showing 3 changed files with 14 additions and 9 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: c9ce7dbdbf25d7245ead1923c11620d4c8013592
refs/heads/master: eeed66e3a50f4d23d542498b17861ffadcdaf8ec
4 changes: 2 additions & 2 deletions trunk/arch/arm/mach-exynos/include/mach/irqs.h
Original file line number Diff line number Diff line change
Expand Up @@ -320,6 +320,8 @@
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
#define EXYNOS5_IRQ_NFCON IRQ_SPI(116)

#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
Expand Down Expand Up @@ -399,8 +401,6 @@
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)

#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
#define EXYNOS5_IRQ_MCT_L0 COMBINER_IRQ(23, 1)
#define EXYNOS5_IRQ_MCT_L1 COMBINER_IRQ(23, 2)
#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_MCT_G2 COMBINER_IRQ(23, 5)
Expand Down
17 changes: 11 additions & 6 deletions trunk/arch/arm/mach-exynos/mct.c
Original file line number Diff line number Diff line change
Expand Up @@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
int mct_lx_irq;

mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
Expand All @@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)

if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L0;
setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick0_event_irq);
} else {
mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
evt->irq = EXYNOS4_IRQ_MCT_L1;
setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
evt->irq = mct_lx_irq;
setup_irq(mct_lx_irq, &mct_tick1_event_irq);
irq_set_affinity(mct_lx_irq, cpumask_of(1));
}
} else {
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
Expand Down Expand Up @@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)

static void __init exynos4_timer_init(void)
{
if (soc_is_exynos4210())
if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
mct_int_type = MCT_INT_SPI;
else
mct_int_type = MCT_INT_PPI;
Expand Down

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