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[POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx
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Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and
PCIe on 85xx/86xx.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Zang Roy-r61911 authored and Kumar Gala committed Jul 23, 2007
1 parent 55c4499 commit 9ac4dd3
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Showing 5 changed files with 187 additions and 226 deletions.
8 changes: 4 additions & 4 deletions arch/powerpc/boot/dts/mpc8641_hpcn.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -211,8 +211,8 @@
interrupt-parent = <&mpic>;
};

pci@8000 {
compatible = "86xx";
pcie@8000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
Expand Down Expand Up @@ -399,8 +399,8 @@

};

pci@9000 {
compatible = "86xx";
pcie@9000 {
compatible = "fsl,mpc8641-pcie";
device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>;
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5 changes: 0 additions & 5 deletions arch/powerpc/platforms/86xx/mpc86xx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,11 +15,6 @@
* mpc86xx_* files. Mostly for use by mpc86xx_setup().
*/

extern int mpc86xx_add_bridge(struct device_node *dev);

extern int mpc86xx_exclude_device(struct pci_controller *hose,
u_char bus, u_char devfn);

extern void __init mpc86xx_smp_init(void);

#endif /* __MPC86XX_H__ */
11 changes: 9 additions & 2 deletions arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
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Original file line number Diff line number Diff line change
Expand Up @@ -31,6 +31,7 @@

#include <asm/mpic.h>

#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>

#include "mpc86xx.h"
Expand Down Expand Up @@ -344,8 +345,14 @@ mpc86xx_hpcn_setup_arch(void)
}

#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
mpc86xx_add_bridge(np);
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) {
struct resource rsrc;
of_address_to_resource(np, 0, &rsrc);
if ((rsrc.start & 0xfffff) == 0x8000)
fsl_add_bridge(np, 1);
else
fsl_add_bridge(np, 0);
}
#endif

printk("MPC86xx HPCN board from Freescale Semiconductor\n");
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244 changes: 105 additions & 139 deletions arch/powerpc/sysdev/fsl_pci.c
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Original file line number Diff line number Diff line change
@@ -1,136 +1,98 @@
/*
* MPC86XX pci setup code
* MPC85xx/86xx PCI/PCIE support routing.
*
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
* Copyright 2007 Freescale Semiconductor, Inc
*
* Copyright 2006 Freescale Semiconductor Inc.
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
* Recode: ZHANG WEI <wei.zhang@freescale.com>
* Rewrite the routing for Frescale PCI and PCI Express
* Roy Zang <tie-fei.zang@freescale.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/

#include <linux/types.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/serial.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/bootmem.h>

#include <asm/system.h>
#include <asm/atomic.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>

#include "../platforms/86xx/mpc86xx.h"

#undef DEBUG

#ifdef DEBUG
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
#else
#define DBG(fmt, args...)
#endif

struct pcie_outbound_window_regs {
uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
char res1[4];
uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
char res2[12];
};

struct pcie_inbound_window_regs {
uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
char res1[4];
uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
char res2[12];
};

static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
/* atmu setup for fsl pci/pcie controller */
void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
{
volatile struct ccsr_pex *pcie;
volatile struct pcie_outbound_window_regs *pcieow;
volatile struct pcie_inbound_window_regs *pcieiw;
int i = 0;
struct ccsr_pci __iomem *pci;
int i;

DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
rsrc->end - rsrc->start + 1);
pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);

/* Disable all windows (except pexowar0 since its ignored) */
pcie->pexowar1 = 0;
pcie->pexowar2 = 0;
pcie->pexowar3 = 0;
pcie->pexowar4 = 0;
pcie->pexiwar1 = 0;
pcie->pexiwar2 = 0;
pcie->pexiwar3 = 0;

pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;

/* Setup outbound MEM window */
for(i = 0; i < 3; i++)
if (hose->mem_resources[i].flags & IORESOURCE_MEM){
DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
hose->mem_resources[i].start,
hose->mem_resources[i].end
- hose->mem_resources[i].start + 1);
pcieow->pexotar = (hose->mem_resources[i].start) >> 12
& 0x000fffff;
pcieow->pexotear = 0;
pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
& 0x000fffff;
/* Enable, Mem R/W */
pcieow->pexowar = 0x80044000 |
(__ilog2(hose->mem_resources[i].end
- hose->mem_resources[i].start + 1)
- 1);
pcieow++;
}

/* Setup outbound IO window */
if (hose->io_resource.flags & IORESOURCE_IO){
DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
hose->io_resource.start,
hose->io_resource.end - hose->io_resource.start + 1,
hose->io_base_phys);
pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
pcieow->pexotear = 0;
pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
/* Enable, IO R/W */
pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
- hose->io_resource.start + 1) - 1);
}

/* Setup 2G inbound Memory Window @ 0 */
pcieiw->pexitar = 0x00000000;
pcieiw->pexiwbar = 0x00000000;
/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
pcieiw->pexiwar = 0xa0f5501e;
pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);

/* Disable all windows (except powar0 since its ignored) */
for(i = 1; i < 5; i++)
out_be32(&pci->pow[i].powar, 0);
for(i = 0; i < 3; i++)
out_be32(&pci->piw[i].piwar, 0);

/* Setup outbound MEM window */
for(i = 0; i < 3; i++)
if (hose->mem_resources[i].flags & IORESOURCE_MEM){
pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
hose->mem_resources[i].start,
hose->mem_resources[i].end
- hose->mem_resources[i].start + 1);
out_be32(&pci->pow[i+1].potar,
(hose->mem_resources[i].start >> 12)
& 0x000fffff);
out_be32(&pci->pow[i+1].potear, 0);
out_be32(&pci->pow[i+1].powbar,
(hose->mem_resources[i].start >> 12)
& 0x000fffff);
/* Enable, Mem R/W */
out_be32(&pci->pow[i+1].powar, 0x80044000
| (__ilog2(hose->mem_resources[i].end
- hose->mem_resources[i].start + 1) - 1));
}

/* Setup outbound IO window */
if (hose->io_resource.flags & IORESOURCE_IO){
pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
hose->io_resource.start,
hose->io_resource.end - hose->io_resource.start + 1,
hose->io_base_phys);
out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
& 0x000fffff);
out_be32(&pci->pow[i+1].potear, 0);
out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
& 0x000fffff);
/* Enable, IO R/W */
out_be32(&pci->pow[i+1].powar, 0x80088000
| (__ilog2(hose->io_resource.end
- hose->io_resource.start + 1) - 1));
}

/* Setup 2G inbound Memory Window @ 1 */
out_be32(&pci->piw[2].pitar, 0x00000000);
out_be32(&pci->piw[2].piwbar,0x00000000);
out_be32(&pci->piw[2].piwar, PIWAR_2G);
}

static void __init
mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
void __init setup_pci_cmd(struct pci_controller *hose)
{
u16 cmd;

DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
pcie_offset, pcie_size);

early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
| PCI_COMMAND_IO;
| PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);

early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
}

Expand Down Expand Up @@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
}
}

int __init fsl_pcie_check_link(struct pci_controller *hose)
{
u16 val;
early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return 1;
return 0;
}

DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);

#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
#define PCIE_LTSSM_L0 0x16 /* L0 state */

int __init mpc86xx_add_bridge(struct device_node *dev)
int __init fsl_add_bridge(struct device_node *dev, int is_primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int has_address = 0;
int primary = 0;
u16 val;

DBG("Adding PCIE host bridge %s\n", dev->full_name);
pr_debug("Adding PCI host bridge %s\n", dev->full_name);

/* Fetch host bridge registers address */
has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
if (of_address_to_resource(dev, 0, &rsrc)) {
printk(KERN_WARNING "Can't get pci register base!");
return -ENOMEM;
}

/* Get bus range if any */
bus_range = of_get_property(dev, "bus-range", &len);
if (bus_range == NULL || len < 2 * sizeof(int))
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
" bus 0\n", dev->full_name);

pci_assign_all_buses = 1;
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;

hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;

hose->first_busno = bus_range ? bus_range[0] : 0x0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;

setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);

/* Probe the hose link training status */
early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
if (val < PCIE_LTSSM_L0)
return -ENXIO;
/* check PCI express bridge */
if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;

/* Setup the PCIE host controller. */
mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
setup_pci_cmd(hose);

if ((rsrc.start & 0xfffff) == 0x8000)
primary = 1;
/* check PCI express link status */
if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
if (fsl_pcie_check_link(hose))
return -ENXIO;

printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
"Firmware bus number: %d->%d\n",
(unsigned long) rsrc.start,
hose->first_busno, hose->last_busno);
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
"Firmware bus number: %d->%d\n",
(unsigned long long)rsrc.start, hose->first_busno,
hose->last_busno);

DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
hose, hose->cfg_addr, hose->cfg_data);

/* Interpret the "ranges" property */
/* This also maps the I/O region and sets isa_io/mem_base */
pci_process_bridge_OF_ranges(hose, dev, primary);
pci_process_bridge_OF_ranges(hose, dev, is_primary);

/* Setup PEX window registers */
setup_pcie_atmu(hose, &rsrc);
setup_pci_atmu(hose, &rsrc);

return 0;
}

DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
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