---

yaml
---
r: 91205
b: refs/heads/master
c: 9dd0b19
h: refs/heads/master
i:
  91203: 7981e85
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 159ffb3a04f6bc619643af680df406faafd0199d
+refs/heads/master: 9dd0b194bf6804b1998f0fe261b2606ec7b58d72

trunk/arch/arm/Kconfig

@@ -377,7 +377,7 @@ config ARCH_MXC
 	help
 	  Support for Freescale MXC/iMX-based family of processors
 
-config ARCH_ORION
+config ARCH_ORION5X
 	bool "Marvell Orion"
 	depends on MMU
 	select PCI
@@ -386,7 +386,8 @@ config ARCH_ORION
 	select GENERIC_CLOCKEVENTS
 	select PLAT_ORION
 	help
-	  Support for Marvell Orion System on Chip family.
+	  Support for the following Marvell Orion 5x series SoCs:
+	  Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.)
 
 config ARCH_PNX4008
 	bool "Philips Nexperia PNX4008 Mobile"
@@ -517,7 +518,7 @@ source "arch/arm/mach-omap1/Kconfig"
 
 source "arch/arm/mach-omap2/Kconfig"
 
-source "arch/arm/mach-orion/Kconfig"
+source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"

trunk/arch/arm/Makefile

@@ -139,7 +139,7 @@ endif
  machine-$(CONFIG_ARCH_KS8695)     := ks8695
   incdir-$(CONFIG_ARCH_MXC)	   := mxc
  machine-$(CONFIG_ARCH_MX3)	   := mx3
- machine-$(CONFIG_ARCH_ORION)	   := orion
+ machine-$(CONFIG_ARCH_ORION5X)	   := orion5x
  machine-$(CONFIG_ARCH_MSM7X00A)   := msm
 
 ifeq ($(CONFIG_ARCH_EBSA110),y)

trunk/arch/arm/configs/orion_defconfig → trunk/arch/arm/configs/orion5x_defconfig

@@ -140,7 +140,7 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_MXC is not set
-CONFIG_ARCH_ORION=y
+CONFIG_ARCH_ORION5X=y
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
 # CONFIG_ARCH_RPC is not set

trunk/arch/arm/mach-orion/Kconfig → trunk/arch/arm/mach-orion5x/Kconfig

@@ -1,4 +1,4 @@
-if ARCH_ORION
+if ARCH_ORION5X
 
 menu "Orion Implementations"
 

trunk/arch/arm/mach-orion/addr-map.c → trunk/arch/arm/mach-orion5x/addr-map.c

@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-orion/addr-map.c
+ * arch/arm/mach-orion5x/addr-map.c
  *
- * Address map functions for Marvell Orion System On Chip
+ * Address map functions for Marvell Orion 5x SoCs
  *
  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
  *
@@ -29,7 +29,7 @@
  * Setup access to PCI and PCI-E IO/MEM space is issued by this file.
  * Setup access to various devices located on the device bus interface (e.g.
  * flashes, RTC, etc) should be issued by machine-setup.c according to
- * specific board population (by using orion_setup_*_win()).
+ * specific board population (by using orion5x_setup_*_win()).
  *
  * Non-CPU Masters address decoding --
  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
@@ -66,8 +66,8 @@
 /*
  * Helpers to get DDR bank info
  */
-#define DDR_BASE_CS(n)		ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n)		ORION_DDR_REG(0x1504 + ((n) * 8))
+#define DDR_BASE_CS(n)		ORION5X_DDR_REG(0x1500 + ((n) * 8))
+#define DDR_SIZE_CS(n)		ORION5X_DDR_REG(0x1504 + ((n) * 8))
 #define DDR_MAX_CS		4
 #define DDR_REG_TO_SIZE(reg)	(((reg) | 0xffffff) + 1)
 #define DDR_REG_TO_BASE(reg)	((reg) & 0xff000000)
@@ -76,30 +76,30 @@
 /*
  * CPU Address Decode Windows registers
  */
-#define CPU_WIN_CTRL(n)		ORION_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)		ORION_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)	ORION_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
+#define CPU_WIN_CTRL(n)		ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
+#define CPU_WIN_BASE(n)		ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
+#define CPU_WIN_REMAP_LO(n)	ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
+#define CPU_WIN_REMAP_HI(n)	ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
 
 /*
  * Gigabit Ethernet Address Decode Windows registers
  */
-#define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win)	ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win)	ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN		ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT		ORION_ETH_REG(0x294)
+#define ETH_WIN_BASE(win)	ORION5X_ETH_REG(0x200 + ((win) * 8))
+#define ETH_WIN_SIZE(win)	ORION5X_ETH_REG(0x204 + ((win) * 8))
+#define ETH_WIN_REMAP(win)	ORION5X_ETH_REG(0x280 + ((win) * 4))
+#define ETH_WIN_EN		ORION5X_ETH_REG(0x290)
+#define ETH_WIN_PROT		ORION5X_ETH_REG(0x294)
 #define ETH_MAX_WIN		6
 #define ETH_MAX_REMAP_WIN	4
 
 
-struct mbus_dram_target_info orion_mbus_dram_info;
+struct mbus_dram_target_info orion5x_mbus_dram_info;
 
-static int __init orion_cpu_win_can_remap(int win)
+static int __init orion5x_cpu_win_can_remap(int win)
 {
 	u32 dev, rev;
 
-	orion_pcie_id(&dev, &rev);
+	orion5x_pcie_id(&dev, &rev);
 	if ((dev == MV88F5281_DEV_ID && win < 4)
 	    || (dev == MV88F5182_DEV_ID && win < 2)
 	    || (dev == MV88F5181_DEV_ID && win < 2))
@@ -111,20 +111,20 @@ static int __init orion_cpu_win_can_remap(int win)
 static void __init setup_cpu_win(int win, u32 base, u32 size,
 				 u8 target, u8 attr, int remap)
 {
-	orion_write(CPU_WIN_BASE(win), base & 0xffff0000);
-	orion_write(CPU_WIN_CTRL(win),
+	orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
+	orion5x_write(CPU_WIN_CTRL(win),
 		((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
 
-	if (orion_cpu_win_can_remap(win)) {
+	if (orion5x_cpu_win_can_remap(win)) {
 		if (remap < 0)
 			remap = base;
 
-		orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
-		orion_write(CPU_WIN_REMAP_HI(win), 0);
+		orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
+		orion5x_write(CPU_WIN_REMAP_HI(win), 0);
 	}
 }
 
-void __init orion_setup_cpu_mbus_bridge(void)
+void __init orion5x_setup_cpu_mbus_bridge(void)
 {
 	int i;
 	int cs;
@@ -133,30 +133,30 @@ void __init orion_setup_cpu_mbus_bridge(void)
 	 * First, disable and clear windows.
 	 */
 	for (i = 0; i < 8; i++) {
-		orion_write(CPU_WIN_BASE(i), 0);
-		orion_write(CPU_WIN_CTRL(i), 0);
-		if (orion_cpu_win_can_remap(i)) {
-			orion_write(CPU_WIN_REMAP_LO(i), 0);
-			orion_write(CPU_WIN_REMAP_HI(i), 0);
+		orion5x_write(CPU_WIN_BASE(i), 0);
+		orion5x_write(CPU_WIN_CTRL(i), 0);
+		if (orion5x_cpu_win_can_remap(i)) {
+			orion5x_write(CPU_WIN_REMAP_LO(i), 0);
+			orion5x_write(CPU_WIN_REMAP_HI(i), 0);
 		}
 	}
 
 	/*
 	 * Setup windows for PCI+PCIe IO+MEM space.
 	 */
-	setup_cpu_win(0, ORION_PCIE_IO_PHYS_BASE, ORION_PCIE_IO_SIZE,
-		TARGET_PCIE, ATTR_PCIE_IO, ORION_PCIE_IO_BUS_BASE);
-	setup_cpu_win(1, ORION_PCI_IO_PHYS_BASE, ORION_PCI_IO_SIZE,
-		TARGET_PCI, ATTR_PCI_IO, ORION_PCI_IO_BUS_BASE);
-	setup_cpu_win(2, ORION_PCIE_MEM_PHYS_BASE, ORION_PCIE_MEM_SIZE,
+	setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+		TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
+	setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
+		TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
+	setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
 		TARGET_PCIE, ATTR_PCIE_MEM, -1);
-	setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE,
+	setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
 		TARGET_PCI, ATTR_PCI_MEM, -1);
 
 	/*
 	 * Setup MBUS dram target info.
 	 */
-	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+	orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
 	for (i = 0, cs = 0; i < 4; i++) {
 		u32 base = readl(DDR_BASE_CS(i));
@@ -168,73 +168,73 @@ void __init orion_setup_cpu_mbus_bridge(void)
 		if (size & 1) {
 			struct mbus_dram_window *w;
 
-			w = &orion_mbus_dram_info.cs[cs++];
+			w = &orion5x_mbus_dram_info.cs[cs++];
 			w->cs_index = i;
 			w->mbus_attr = 0xf & ~(1 << i);
 			w->base = base & 0xff000000;
 			w->size = (size | 0x00ffffff) + 1;
 		}
 	}
-	orion_mbus_dram_info.num_cs = cs;
+	orion5x_mbus_dram_info.num_cs = cs;
 }
 
-void __init orion_setup_dev_boot_win(u32 base, u32 size)
+void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
 	setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 
-void __init orion_setup_dev0_win(u32 base, u32 size)
+void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
 	setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 
-void __init orion_setup_dev1_win(u32 base, u32 size)
+void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
 	setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 
-void __init orion_setup_dev2_win(u32 base, u32 size)
+void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
 	setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 
-void __init orion_setup_pcie_wa_win(u32 base, u32 size)
+void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
 	setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
 
-void __init orion_setup_eth_wins(void)
+void __init orion5x_setup_eth_wins(void)
 {
 	int i;
 
 	/*
 	 * First, disable and clear windows
 	 */
 	for (i = 0; i < ETH_MAX_WIN; i++) {
-		orion_write(ETH_WIN_BASE(i), 0);
-		orion_write(ETH_WIN_SIZE(i), 0);
-		orion_setbits(ETH_WIN_EN, 1 << i);
-		orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
+		orion5x_write(ETH_WIN_BASE(i), 0);
+		orion5x_write(ETH_WIN_SIZE(i), 0);
+		orion5x_setbits(ETH_WIN_EN, 1 << i);
+		orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
 		if (i < ETH_MAX_REMAP_WIN)
-			orion_write(ETH_WIN_REMAP(i), 0);
+			orion5x_write(ETH_WIN_REMAP(i), 0);
 	}
 
 	/*
 	 * Setup windows for DDR banks.
 	 */
 	for (i = 0; i < DDR_MAX_CS; i++) {
 		u32 base, size;
-		size = orion_read(DDR_SIZE_CS(i));
-		base = orion_read(DDR_BASE_CS(i));
+		size = orion5x_read(DDR_SIZE_CS(i));
+		base = orion5x_read(DDR_BASE_CS(i));
 		if (size & DDR_BANK_EN) {
 			base = DDR_REG_TO_BASE(base);
 			size = DDR_REG_TO_SIZE(size);
-			orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
-			orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
+			orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
+			orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
 					(ATTR_DDR_CS(i) << 8) |
 					TARGET_DDR);
-			orion_clrbits(ETH_WIN_EN, 1 << i);
-			orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
+			orion5x_clrbits(ETH_WIN_EN, 1 << i);
+			orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
 		}
 	}
 }