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Antoine Tenart says: ==================== ARM: Berlin: Ethernet support This series introduce support for the Ethernet controller on Berlin SoCs, using the existing pxa168 Ethernet driver. In order to do this, DT support is added to the driver alongside some other modifications and fixes. This has been tested on a Berlin BG2Q DMP board. Changes since v5: - fixed the build when building the driver as a module Changes since v4: - removed the phy-addr property and added a phy subnode - added COMPILE_TEST for the pxa168_eth driver Changes since v3: - moved the addition of pxa168_eth_get_mac_address() to the patch using it first Changes since v2: - reworked how the MAC address is configured - made the clock anonymous Changes since v1: - removed custom Berlin Ethernet driver - used the pxa168 Ethernet driver instead - made modifications to the pxa168 driver (DT support, fixes) ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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* Marvell PXA168 Ethernet Controller | ||
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Required properties: | ||
- compatible: should be "marvell,pxa168-eth". | ||
- reg: address and length of the register set for the device. | ||
- interrupts: interrupt for the device. | ||
- clocks: pointer to the clock for the device. | ||
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Optional properties: | ||
- port-id: Ethernet port number. Should be '0','1' or '2'. | ||
- #address-cells: must be 1 when using sub-nodes. | ||
- #size-cells: must be 0 when using sub-nodes. | ||
- phy-handle: see ethernet.txt file in the same directory. | ||
- local-mac-address: see ethernet.txt file in the same directory. | ||
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Sub-nodes: | ||
Each PHY can be represented as a sub-node. This is not mandatory. | ||
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Sub-nodes required properties: | ||
- reg: the MDIO address of the PHY. | ||
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Example: | ||
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eth0: ethernet@f7b90000 { | ||
compatible = "marvell,pxa168-eth"; | ||
reg = <0xf7b90000 0x10000>; | ||
clocks = <&chip CLKID_GETH0>; | ||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | ||
#address-cells = <1>; | ||
#size-cells = <0>; | ||
phy-handle = <ðphy0>; | ||
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ethphy0: ethernet-phy@0 { | ||
reg = <0>; | ||
}; | ||
}; |
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&uart0 { | ||
status = "okay"; | ||
}; | ||
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ð0 { | ||
status = "okay"; | ||
}; |
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