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MIPS: Alchemy: devboard register abstraction
All Alchemy development boards have external CPLDs with a few registers in them. They all share an identical register layout with only a few minor differences (except the PB1000) in bit functions and base addresses. This patch - adds a primitive facility to initialize and use these external registers, - replaces all occurrences of bcsr->xxx accesses with calls to the new functions (the pb1200 cascade irq handling code is special). - collects BCSR register information scattered throughout the board headers in a central place. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Manuel Lauss
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Ralf Baechle
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Feb 27, 2010
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,76 @@ | ||
| /* | ||
| * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction. | ||
| * | ||
| * All Alchemy development boards (except, of course, the weird PB1000) | ||
| * have a few registers in a CPLD with standardised layout; they mostly | ||
| * only differ in base address. | ||
| * All registers are 16bits wide with 32bit spacing. | ||
| */ | ||
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| #include <linux/module.h> | ||
| #include <linux/spinlock.h> | ||
| #include <asm/addrspace.h> | ||
| #include <asm/io.h> | ||
| #include <asm/mach-db1x00/bcsr.h> | ||
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| static struct bcsr_reg { | ||
| void __iomem *raddr; | ||
| spinlock_t lock; | ||
| } bcsr_regs[BCSR_CNT]; | ||
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| void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys) | ||
| { | ||
| int i; | ||
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| bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys)); | ||
| bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys)); | ||
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| for (i = 0; i < BCSR_CNT; i++) { | ||
| if (i >= BCSR_HEXLEDS) | ||
| bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys + | ||
| (0x04 * (i - BCSR_HEXLEDS)); | ||
| else | ||
| bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys + | ||
| (0x04 * i); | ||
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| spin_lock_init(&bcsr_regs[i].lock); | ||
| } | ||
| } | ||
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| unsigned short bcsr_read(enum bcsr_id reg) | ||
| { | ||
| unsigned short r; | ||
| unsigned long flags; | ||
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| spin_lock_irqsave(&bcsr_regs[reg].lock, flags); | ||
| r = __raw_readw(bcsr_regs[reg].raddr); | ||
| spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); | ||
| return r; | ||
| } | ||
| EXPORT_SYMBOL_GPL(bcsr_read); | ||
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| void bcsr_write(enum bcsr_id reg, unsigned short val) | ||
| { | ||
| unsigned long flags; | ||
|
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| spin_lock_irqsave(&bcsr_regs[reg].lock, flags); | ||
| __raw_writew(val, bcsr_regs[reg].raddr); | ||
| wmb(); | ||
| spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); | ||
| } | ||
| EXPORT_SYMBOL_GPL(bcsr_write); | ||
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| void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set) | ||
| { | ||
| unsigned short r; | ||
| unsigned long flags; | ||
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| spin_lock_irqsave(&bcsr_regs[reg].lock, flags); | ||
| r = __raw_readw(bcsr_regs[reg].raddr); | ||
| r &= ~clr; | ||
| r |= set; | ||
| __raw_writew(r, bcsr_regs[reg].raddr); | ||
| wmb(); | ||
| spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags); | ||
| } | ||
| EXPORT_SYMBOL_GPL(bcsr_mod); |
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