---

yaml
---
r: 91608
b: refs/heads/master
c: 1a9ebc0
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 8bdf573334102f44c7ad191422baf851fecf25e8
+refs/heads/master: 1a9ebc0cd2b3bb4450834e564722630fbc40611b

trunk/arch/powerpc/platforms/83xx/mpc83xx.h

@@ -16,6 +16,7 @@
 #define MPC83XX_SCCR_USB_DRCM_10   0x00200000
 #define MPC8315_SCCR_USB_MASK      0x00c00000
 #define MPC8315_SCCR_USB_DRCM_11   0x00c00000
+#define MPC8315_SCCR_USB_DRCM_01   0x00400000
 #define MPC837X_SCCR_USB_DRCM_11   0x00c00000
 
 /* system i/o configuration register low */
@@ -37,6 +38,7 @@
 /* USB Control Register */
 #define FSL_USB2_CONTROL_OFFS      0x500
 #define CONTROL_UTMI_PHY_EN        0x00000200
+#define CONTROL_REFSEL_24MHZ       0x00000040
 #define CONTROL_REFSEL_48MHZ       0x00000080
 #define CONTROL_PHY_CLK_SEL_ULPI   0x00000400
 #define CONTROL_OTG_PORT           0x00000020

trunk/arch/powerpc/platforms/83xx/usb.c

@@ -129,7 +129,7 @@ int mpc831x_usb_cfg(void)
 	if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
 		clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
 		                MPC8315_SCCR_USB_MASK,
-		                MPC8315_SCCR_USB_DRCM_11);
+		                MPC8315_SCCR_USB_DRCM_01);
 	else
 		clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
 		                MPC83XX_SCCR_USB_MASK,
@@ -164,9 +164,15 @@ int mpc831x_usb_cfg(void)
 	/* Using on-chip PHY */
 	if (prop && (!strcmp(prop, "utmi_wide") ||
 		     !strcmp(prop, "utmi"))) {
-		/* Set UTMI_PHY_EN, REFSEL to 48MHZ */
+		u32 refsel;
+
+		if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
+			refsel = CONTROL_REFSEL_24MHZ;
+		else
+			refsel = CONTROL_REFSEL_48MHZ;
+		/* Set UTMI_PHY_EN and REFSEL */
 		out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
-				CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ);
+				CONTROL_UTMI_PHY_EN | refsel);
 	/* Using external UPLI PHY */
 	} else if (prop && !strcmp(prop, "ulpi")) {
 		/* Set PHY_CLK_SEL to ULPI */