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cpufreq: exynos: Use APLL_FREQ macro for cpu divider value
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Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Jonghwan Choi authored and Kukjin Kim committed Dec 23, 2012
1 parent 857d90f commit 9d0554f
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Showing 4 changed files with 136 additions and 561 deletions.
16 changes: 16 additions & 0 deletions arch/arm/mach-exynos/include/mach/cpufreq.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,22 @@ enum cpufreq_level_index {
L20,
};

#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
{ \
.freq = (f) * 1000, \
.clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
(a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
.clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
.mps = ((m) << 16 | (p) << 8 | (s)), \
}

struct apll_freq {
unsigned int freq;
u32 clk_div_cpu0;
u32 clk_div_cpu1;
u32 mps;
};

struct exynos_dvfs_info {
unsigned long mpll_freq_khz;
unsigned int pll_safe_idx;
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135 changes: 25 additions & 110 deletions drivers/cpufreq/exynos4210-cpufreq.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,94 +20,37 @@
#include <mach/regs-clock.h>
#include <mach/cpufreq.h>

#define CPUFREQ_LEVEL_END L5

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

struct cpufreq_clkdiv {
unsigned int index;
unsigned int clkdiv;
};

static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
static unsigned int exynos4210_volt_table[] = {
1250000, 1150000, 1050000, 975000, 950000,
};


static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];

static struct cpufreq_frequency_table exynos4210_freq_table[] = {
{L0, 1200*1000},
{L1, 1000*1000},
{L2, 800*1000},
{L3, 500*1000},
{L4, 200*1000},
{L0, 1200 * 1000},
{L1, 1000 * 1000},
{L2, 800 * 1000},
{L3, 500 * 1000},
{L4, 200 * 1000},
{0, CPUFREQ_TABLE_END},
};

static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
static struct apll_freq apll_freq_4210[] = {
/*
* Clock divider value for following
* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
* DIVATB, DIVPCLK_DBG, DIVAPLL }
* values:
* freq
* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
* clock divider for COPY, HPM, RESERVED
* PLL M, P, S
*/

/* ARM L0: 1200MHz */
{ 0, 3, 7, 3, 4, 1, 7 },

/* ARM L1: 1000MHz */
{ 0, 3, 7, 3, 4, 1, 7 },

/* ARM L2: 800MHz */
{ 0, 3, 7, 3, 3, 1, 7 },

/* ARM L3: 500MHz */
{ 0, 3, 7, 3, 3, 1, 7 },

/* ARM L4: 200MHz */
{ 0, 1, 3, 1, 3, 1, 0 },
};

static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
/*
* Clock divider value for following
* { DIVCOPY, DIVHPM }
*/

/* ARM L0: 1200MHz */
{ 5, 0 },

/* ARM L1: 1000MHz */
{ 4, 0 },

/* ARM L2: 800MHz */
{ 3, 0 },

/* ARM L3: 500MHz */
{ 3, 0 },

/* ARM L4: 200MHz */
{ 3, 0 },
};

static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
/* APLL FOUT L0: 1200MHz */
((150 << 16) | (3 << 8) | 1),

/* APLL FOUT L1: 1000MHz */
((250 << 16) | (6 << 8) | 1),

/* APLL FOUT L2: 800MHz */
((200 << 16) | (6 << 8) | 1),

/* APLL FOUT L3: 500MHz */
((250 << 16) | (6 << 8) | 2),

/* APLL FOUT L4: 200MHz */
((200 << 16) | (6 << 8) | 3),
APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
};

static void exynos4210_set_clkdiv(unsigned int div_index)
Expand All @@ -116,7 +59,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)

/* Change Divider - CPU0 */

tmp = exynos4210_clkdiv_table[div_index].clkdiv;
tmp = apll_freq_4210[div_index].clk_div_cpu0;

__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);

Expand All @@ -126,12 +69,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)

/* Change Divider - CPU1 */

tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);

tmp &= ~((0x7 << 4) | 0x7);

tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
(clkdiv_cpu1[div_index][1] << 0));
tmp = apll_freq_4210[div_index].clk_div_cpu1;

__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);

Expand Down Expand Up @@ -159,7 +97,7 @@ static void exynos4210_set_apll(unsigned int index)
/* 3. Change PLL PMS values */
tmp = __raw_readl(EXYNOS4_APLL_CON0);
tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
tmp |= exynos4210_apll_pms_table[index];
tmp |= apll_freq_4210[index].mps;
__raw_writel(tmp, EXYNOS4_APLL_CON0);

/* 4. wait_lock_time */
Expand All @@ -178,8 +116,8 @@ static void exynos4210_set_apll(unsigned int index)

bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
{
unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
unsigned int old_pm = apll_freq_4210[old_index].mps >> 8;
unsigned int new_pm = apll_freq_4210[new_index].mps >> 8;

return (old_pm == new_pm) ? 0 : 1;
}
Expand All @@ -197,7 +135,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
/* 2. Change just s value in apll m,p,s value */
tmp = __raw_readl(EXYNOS4_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
tmp |= apll_freq_4210[new_index].mps & 0x7;
__raw_writel(tmp, EXYNOS4_APLL_CON0);
} else {
/* Clock Configuration Procedure */
Expand All @@ -211,7 +149,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
/* 1. Change just s value in apll m,p,s value */
tmp = __raw_readl(EXYNOS4_APLL_CON0);
tmp &= ~(0x7 << 0);
tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
tmp |= apll_freq_4210[new_index].mps & 0x7;
__raw_writel(tmp, EXYNOS4_APLL_CON0);

/* 2. Change the system clock divider values */
Expand All @@ -228,8 +166,6 @@ static void exynos4210_set_frequency(unsigned int old_index,

int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
{
int i;
unsigned int tmp;
unsigned long rate;

cpu_clk = clk_get(NULL, "armclk");
Expand All @@ -250,29 +186,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
if (IS_ERR(mout_apll))
goto err_mout_apll;

tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);

for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
EXYNOS4_CLKDIV_CPU0_ATB_MASK |
EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
EXYNOS4_CLKDIV_CPU0_APLL_MASK);

tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
(clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
(clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
(clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
(clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
(clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
(clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));

exynos4210_clkdiv_table[i].clkdiv = tmp;
}

info->mpll_freq_khz = rate;
/* 800Mhz */
info->pll_safe_idx = L2;
info->cpu_clk = cpu_clk;
info->volt_table = exynos4210_volt_table;
Expand Down
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