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Merge branch 'renesas-soc' into renesas-board
* renesas-soc: (31 commits) ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config ARM: shmobile: Take cpuidle dependencies into account correctly ARM: mach-shmobile: sh7377 generic board support via DT ARM: mach-shmobile: r8a7740 generic board support via DT ARM: shmobile: sh7372: completely switch over to using pm-rmobile API ARM: shmobile: ap4evb: switch to using pm-rmobile API ARM: shmobile: mackerel: switch to using pm-rmobile API ARM: shmobile: sh7372: add pm-rmobile domain support ARM: shmobile: r8a7740: add A4LC pm domain support ARM: shmobile: r8a7740: add A3SP pm domain support ARM: shmobile: r8a7740: add A4S pm domain support ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control ARM: shmobile: soc-core: add R-mobile PM domain common APIs ARM: shmobile: sh7372 A3SM CPUIdle support ARM: shmobile: Use INTCA with sh7372 A3SM power domain ARM: mach-shmobile: Convert sh_clk_mstp32_register to sh_clk_mstp_register ARM: shmobile: use common DMAEngine definitions on sh7372 ARM: shmobile: use common DMAEngine definitions on sh73a0 ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC ARM: shmobile: sh73a0: add USB clock support ...
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| Original file line number | Diff line number | Diff line change |
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| /* | ||
| * Device Tree Source for the r8a7740 SoC | ||
| * | ||
| * Copyright (C) 2012 Renesas Solutions Corp. | ||
| * | ||
| * This file is licensed under the terms of the GNU General Public License | ||
| * version 2. This program is licensed "as is" without any warranty of any | ||
| * kind, whether express or implied. | ||
| */ | ||
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| /include/ "skeleton.dtsi" | ||
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| / { | ||
| compatible = "renesas,r8a7740"; | ||
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| cpus { | ||
| cpu@0 { | ||
| compatible = "arm,cortex-a9"; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,21 @@ | ||
| /* | ||
| * Device Tree Source for the sh7377 SoC | ||
| * | ||
| * Copyright (C) 2012 Renesas Solutions Corp. | ||
| * | ||
| * This file is licensed under the terms of the GNU General Public License | ||
| * version 2. This program is licensed "as is" without any warranty of any | ||
| * kind, whether express or implied. | ||
| */ | ||
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| /include/ "skeleton.dtsi" | ||
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| / { | ||
| compatible = "renesas,sh7377"; | ||
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| cpus { | ||
| cpu@0 { | ||
| compatible = "arm,cortex-a8"; | ||
| }; | ||
| }; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,84 @@ | ||
| /* | ||
| * SH-ARM CPU-specific DMA definitions, used by both DMA drivers | ||
| * | ||
| * Copyright (C) 2012 Renesas Solutions Corp | ||
| * | ||
| * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | ||
| * | ||
| * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h | ||
| * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de> | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License version 2 as | ||
| * published by the Free Software Foundation. | ||
| */ | ||
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| #ifndef DMA_REGISTER_H | ||
| #define DMA_REGISTER_H | ||
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| /* | ||
| * Direct Memory Access Controller | ||
| */ | ||
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| /* Transmit sizes and respective CHCR register values */ | ||
| enum { | ||
| XMIT_SZ_8BIT = 0, | ||
| XMIT_SZ_16BIT = 1, | ||
| XMIT_SZ_32BIT = 2, | ||
| XMIT_SZ_64BIT = 7, | ||
| XMIT_SZ_128BIT = 3, | ||
| XMIT_SZ_256BIT = 4, | ||
| XMIT_SZ_512BIT = 5, | ||
| }; | ||
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| /* log2(size / 8) - used to calculate number of transfers */ | ||
| static const unsigned int dma_ts_shift[] = { | ||
| [XMIT_SZ_8BIT] = 0, | ||
| [XMIT_SZ_16BIT] = 1, | ||
| [XMIT_SZ_32BIT] = 2, | ||
| [XMIT_SZ_64BIT] = 3, | ||
| [XMIT_SZ_128BIT] = 4, | ||
| [XMIT_SZ_256BIT] = 5, | ||
| [XMIT_SZ_512BIT] = 6, | ||
| }; | ||
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| #define TS_LOW_BIT 0x3 /* --xx */ | ||
| #define TS_HI_BIT 0xc /* xx-- */ | ||
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| #define TS_LOW_SHIFT (3) | ||
| #define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */ | ||
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| #define TS_INDEX2VAL(i) \ | ||
| ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\ | ||
| (((i) & TS_HI_BIT) << TS_HI_SHIFT)) | ||
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| #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz))) | ||
| #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz))) | ||
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| /* | ||
| * USB High-Speed DMAC | ||
| */ | ||
| /* Transmit sizes and respective CHCR register values */ | ||
| enum { | ||
| USBTS_XMIT_SZ_8BYTE = 0, | ||
| USBTS_XMIT_SZ_16BYTE = 1, | ||
| USBTS_XMIT_SZ_32BYTE = 2, | ||
| }; | ||
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| /* log2(size / 8) - used to calculate number of transfers */ | ||
| static const unsigned int dma_usbts_shift[] = { | ||
| [USBTS_XMIT_SZ_8BYTE] = 3, | ||
| [USBTS_XMIT_SZ_16BYTE] = 4, | ||
| [USBTS_XMIT_SZ_32BYTE] = 5, | ||
| }; | ||
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| #define USBTS_LOW_BIT 0x3 /* --xx */ | ||
| #define USBTS_HI_BIT 0x0 /* ---- */ | ||
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| #define USBTS_LOW_SHIFT 6 | ||
| #define USBTS_HI_SHIFT 0 | ||
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| #define USBTS_INDEX2VAL(i) (((i) & 3) << 6) | ||
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| #endif /* DMA_REGISTER_H */ |
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