---

yaml
---
r: 216927
b: refs/heads/master
c: a3fed9b
h: refs/heads/master
i:
  216925: 593d097
  216923: d324e9d
  216919: bf313ad
  216911: 241c048
  216895: 49c998f
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: dcf5ef3f42fbc0c62043b4c466d679fca32f1b9f
+refs/heads/master: a3fed9bc181666df6ecfe9ce34a29d48803f2310

trunk/arch/arm/mach-omap2/sram34xx.S

@@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
 	ldr	r4, [sp, #80]
 	str     r4, omap_sdrc_mr_1_val
 skip_cs1_params:
+	mrc	p15, 0, r8, c1, c0, 0	@ read ctrl register
+	bic	r10, r8, #0x800		@ clear Z-bit, disable branch prediction
+	mcr	p15, 0, r10, c1, c0, 0	@ write ctrl register
 	dsb				@ flush buffered writes to interconnect
-
+	isb				@ prevent speculative exec past here
 	cmp	r3, #1			@ if increasing SDRC clk rate,
 	bleq	configure_sdrc		@ program the SDRC regs early (for RFR)
 	cmp	r1, #SDRC_UNLOCK_DLL	@ set the intended DLL state
@@ -148,6 +151,7 @@ skip_cs1_params:
 	beq	return_to_sdram		@ return to SDRAM code, otherwise,
 	bl	configure_sdrc		@ reprogram SDRC regs now
 return_to_sdram:
+	mcr	p15, 0, r8, c1, c0, 0	@ restore ctrl register
 	isb				@ prevent speculative exec past here
 	mov 	r0, #0 			@ return value
 	ldmfd	sp!, {r1-r12, pc}	@ restore regs and return