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yaml --- r: 905 b: refs/heads/master c: 21e3728 h: refs/heads/master i: 903: 979daf9 v: v3
git-mirror · May 3, 2005 · 9d20395 · 9d20395
1 parent 911f39e
commit 9d20395
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Showing 2 changed files with 25 additions and 1 deletion.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7223a93a5321f84337647aef62ef947afd8df41a
+refs/heads/master: 21e37283909c12e300ab87c20f5addc878cda9f9
diff --git a/trunk/include/asm-ia64/sn/shub_mmr.h b/trunk/include/asm-ia64/sn/shub_mmr.h
@@ -384,6 +384,17 @@
 #define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
 #define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
 
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH1_IPI_ACCESS                           0x0000000110060480
+#define SH2_IPI_ACCESS0                          0x0000000010060c00
+#define SH2_IPI_ACCESS1                          0x0000000010060c80
+#define SH2_IPI_ACCESS2                          0x0000000010060d00
+#define SH2_IPI_ACCESS3                          0x0000000010060d80
+
 /* ==================================================================== */
 /*                        Register "SH_INT_CMPB"                        */
 /*                  RTC Compare Value for Processor B                   */
@@ -429,6 +440,19 @@
 #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
 
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQLP_MMR_DIR_PRIVEC0              0x0000000100030300
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH1_MD_DQRP_MMR_DIR_PRIVEC0              0x0000000100050300
 
 /* ==================================================================== */
 /* Some MMRs are functionally identical (or close enough) on both SHUB1 */