---

yaml --- r: 231821 b: refs/heads/master c: 8ce877a h: refs/heads/master i: 231819: d2e69fb v: v3
git-mirror · Jan 5, 2011 · 9edf102 · 9edf102
1 parent 3c06f9d
commit 9edf102
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Showing 7 changed files with 81 additions and 193 deletions.
diff --git a/[refs] b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 3d461401eb5e3a8c471e92500aebd6c115273fba
+refs/heads/master: 8ce877a8eb8293b5b2c07f259d694026b0f519e4
diff --git a/trunk/arch/m68k/include/asm/cacheflush_no.h b/trunk/arch/m68k/include/asm/cacheflush_no.h
@@ -2,15 +2,15 @@
 #define _M68KNOMMU_CACHEFLUSH_H
 
 /*
- * (C) Copyright 2000-2004, Greg Ungerer <gerg@snapgear.com>
+ * (C) Copyright 2000-2010, Greg Ungerer <gerg@snapgear.com>
  */
 #include <linux/mm.h>
 #include <asm/mcfsim.h>
 
 #define flush_cache_all()			__flush_cache_all()
 #define flush_cache_mm(mm)			do { } while (0)
 #define flush_cache_dup_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	__flush_cache_all()
+#define flush_cache_range(vma, start, end)	do { } while (0)
 #define flush_cache_page(vma, vmaddr)		do { } while (0)
 #ifndef flush_dcache_range
 #define flush_dcache_range(start,len)		__flush_cache_all()
@@ -33,41 +33,13 @@
 #ifndef __flush_cache_all
 static inline void __flush_cache_all(void)
 {
-#if defined(CONFIG_M523x) || defined(CONFIG_M527x)
+#ifdef CACHE_INVALIDATE
 	__asm__ __volatile__ (
-		"movel	#0x81400110, %%d0\n\t"
+		"movel	%0, %%d0\n\t"
 		"movec	%%d0, %%CACR\n\t"
 		"nop\n\t"
-		: : : "d0" );
-#endif /* CONFIG_M523x || CONFIG_M527x */
-#if defined(CONFIG_M528x)
-	__asm__ __volatile__ (
-		"movel	#0x81000200, %%d0\n\t"
-		"movec	%%d0, %%CACR\n\t"
-		"nop\n\t"
-		: : : "d0" );
-#endif /* CONFIG_M528x */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272)
-	__asm__ __volatile__ (
-		"movel	#0x81000100, %%d0\n\t"
-		"movec	%%d0, %%CACR\n\t"
-		"nop\n\t"
-		: : : "d0" );
-#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */
-#ifdef CONFIG_M5249
-	__asm__ __volatile__ (
-		"movel	#0xa1000200, %%d0\n\t"
-		"movec	%%d0, %%CACR\n\t"
-		"nop\n\t"
-		: : : "d0" );
-#endif /* CONFIG_M5249 */
-#ifdef CONFIG_M532x
-	__asm__ __volatile__ (
-		"movel	#0x81000210, %%d0\n\t"
-		"movec	%%d0, %%CACR\n\t"
-		"nop\n\t"
-		: : : "d0" );
-#endif /* CONFIG_M532x */
+		: : "i" (CACHE_INVALIDATE) : "d0" );
+#endif
 }
 #endif /* __flush_cache_all */
 

diff --git a/trunk/arch/m68k/include/asm/m52xxacr.h b/trunk/arch/m68k/include/asm/m52xxacr.h
@@ -52,5 +52,32 @@
 #define ACR_BWE		0x00000020	/* Write buffer enabled */
 #define ACR_WPROTECT	0x00000004	/* Write protect region */
 
+/*
+ * Set the cache controller settings we will use. This code is set to
+ * only use the instruction cache, even on the controllers that support
+ * split cache. (This setup is trying to preserve the existing behavior
+ * for now, in the furture I hope to actually use the split cache mode).
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5249) || defined(CONFIG_M5272)
+#define CACHE_INIT	(CACR_CINV)
+#define CACHE_MODE	(CACR_CENB + CACR_DCM)
+#else
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_INIT	(CACR_CINV + CACR_DISD)
+#define CACHE_MODE	(CACR_CENB + CACR_DISD + CACR_DCM)
+#else
+#define CACHE_INIT	(CACR_CINV + CACR_DISD + CACR_EUSP)
+#define CACHE_MODE	(CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
+#endif
+#endif
+
+#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
+
+#define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
+			 (0x000f0000) + \
+			 (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
+#define ACR1_MODE	0
+
 /****************************************************************************/
 #endif  /* m52xxsim_h */
diff --git a/trunk/arch/m68k/include/asm/m53xxacr.h b/trunk/arch/m68k/include/asm/m53xxacr.h
@@ -48,5 +48,23 @@
 #define ACR_CM_IMPRE	0x00000060	/* Cache inhibited, imprecise */
 #define ACR_WPROTECT	0x00000004	/* Write protect region */
 
+/*
+ * Set the cache controller settings we will use. This default in the
+ * CACR is cache inhibited, we use the ACR register to set cacheing
+ * enabled on the regions we want (eg RAM).
+ */
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_MODE	(CACR_EC + CACR_ESB + CACR_DCM_PRE)
+#else
+#define CACHE_MODE	(CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
+#endif
+
+#define CACHE_INIT	CACR_CINVA
+
+#define ACR0_MODE	((CONFIG_RAMBASE & 0xff000000) + \
+			 (0x000f0000) + \
+			 (ACR_ENABLE + ACR_ANY + ACR_CM_CB))
+#define ACR1_MODE	0
+
 /****************************************************************************/
 #endif  /* m53xxsim_h */
diff --git a/trunk/arch/m68k/include/asm/m54xxacr.h b/trunk/arch/m68k/include/asm/m54xxacr.h
@@ -73,11 +73,16 @@
 #else
 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP)
 #endif
-
 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT)
-
 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY)
 
+#define CACHE_INIT	(CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+#define CACHE_INVALIDATE (CACHE_MODE+CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+#define ACR0_MODE	(0x000f0000+DATA_CACHE_MODE)
+#define ACR1_MODE	0
+#define ACR2_MODE	(0x000f0000+INSN_CACHE_MODE)
+#define ACR3_MODE	0
+
 #ifndef __ASSEMBLY__
 
 #if ((DATA_CACHE_MODE & ACR_CM) == ACR_CM_WT)
@@ -112,7 +117,7 @@ static inline void __m54xx_flush_cache_all(void)
 		: "i" (CACHE_LINE_SIZE),
 		  "i" (DCACHE_SIZE / CACHE_WAYS),
 		  "i" (CACHE_WAYS),
-		  "i" (CACHE_MODE|CACR_DCINVA|CACR_BCINVA|CACR_ICINVA)
+		  "i" (CACHE_INVALIDATE)
 		: "d0", "a0" );
 }
 

diff --git a/trunk/arch/m68k/include/asm/mcfcache.h b/trunk/arch/m68k/include/asm/mcfcache.h
diff --git a/trunk/arch/m68knommu/platform/coldfire/head.S b/trunk/arch/m68knommu/platform/coldfire/head.S
@@ -3,7 +3,7 @@
 /*
  *	head.S -- common startup code for ColdFire CPUs.
  *
- *	(C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com>.
+ *	(C) Copyright 1999-2010, Greg Ungerer <gerg@snapgear.com>.
  */
 
 /*****************************************************************************/
@@ -13,7 +13,6 @@
 #include <linux/init.h>
 #include <asm/asm-offsets.h>
 #include <asm/coldfire.h>
-#include <asm/mcfcache.h>
 #include <asm/mcfsim.h>
 #include <asm/thread_info.h>
 
@@ -173,10 +172,27 @@ _start:
 
 	/*
 	 *	Now that we know what the memory is, lets enable cache
-	 *	and get things moving. This is Coldfire CPU specific.
+	 *	and get things moving. This is Coldfire CPU specific. Not
+	 *	all version cores have identical cache register setup. But
+	 *	it is very similar. Define the exact settings in the headers
+	 *	then the code here is the same for all.
 	 */
-	CACHE_ENABLE				/* enable CPU cache */
-
+	movel	#CACHE_INIT,%d0			/* invalidate whole cache */
+	movec	%d0,%CACR
+	nop
+	movel	#ACR0_MODE,%d0			/* set RAM region for caching */
+	movec	%d0,%ACR0
+	movel	#ACR1_MODE,%d0			/* anything else to cache? */
+	movec	%d0,%ACR1
+#ifdef ACR2_MODE
+	movel	#ACR2_MODE,%d0
+	movec	%d0,%ACR2
+	movel	#ACR3_MODE,%d0
+	movec	%d0,%ACR3
+#endif
+	movel	#CACHE_MODE,%d0			/* enable cache */
+	movec	%d0,%CACR
+	nop
 
 #ifdef CONFIG_ROMFS_FS
 	/*