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Russell King
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| Original file line number | Diff line number | Diff line change |
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| --- | ||
| refs/heads/master: 3ad0920d7b11a88379ec4db186be3eee667c4278 | ||
| refs/heads/master: b78eabde89f9b19d463a77abe420508c0ef29249 |
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| Original file line number | Diff line number | Diff line change |
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| /* | ||
| * include/asm-arm/arch-at91/at91cap9_ddrsdr.h | ||
| * | ||
| * DDR/SDR Controller (DDRSDRC) - System peripherals registers. | ||
| * Based on AT91CAP9 datasheet revision B. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| */ | ||
|
|
||
| #ifndef AT91CAP9_DDRSDR_H | ||
| #define AT91CAP9_DDRSDR_H | ||
|
|
||
| #define AT91_DDRSDRC_MR (AT91_DDRSDRC + 0x00) /* Mode Register */ | ||
| #define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ | ||
| #define AT91_DDRSDRC_MODE_NORMAL 0 | ||
| #define AT91_DDRSDRC_MODE_NOP 1 | ||
| #define AT91_DDRSDRC_MODE_PRECHARGE 2 | ||
| #define AT91_DDRSDRC_MODE_LMR 3 | ||
| #define AT91_DDRSDRC_MODE_REFRESH 4 | ||
| #define AT91_DDRSDRC_MODE_EXT_LMR 5 | ||
| #define AT91_DDRSDRC_MODE_DEEP 6 | ||
|
|
||
| #define AT91_DDRSDRC_RTR (AT91_DDRSDRC + 0x04) /* Refresh Timer Register */ | ||
| #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ | ||
|
|
||
| #define AT91_DDRSDRC_CR (AT91_DDRSDRC + 0x08) /* Configuration Register */ | ||
| #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ | ||
| #define AT91_DDRSDRC_NC_SDR8 (0 << 0) | ||
| #define AT91_DDRSDRC_NC_SDR9 (1 << 0) | ||
| #define AT91_DDRSDRC_NC_SDR10 (2 << 0) | ||
| #define AT91_DDRSDRC_NC_SDR11 (3 << 0) | ||
| #define AT91_DDRSDRC_NC_DDR9 (0 << 0) | ||
| #define AT91_DDRSDRC_NC_DDR10 (1 << 0) | ||
| #define AT91_DDRSDRC_NC_DDR11 (2 << 0) | ||
| #define AT91_DDRSDRC_NC_DDR12 (3 << 0) | ||
| #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ | ||
| #define AT91_DDRSDRC_NR_11 (0 << 2) | ||
| #define AT91_DDRSDRC_NR_12 (1 << 2) | ||
| #define AT91_DDRSDRC_NR_13 (2 << 2) | ||
| #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ | ||
| #define AT91_DDRSDRC_CAS_2 (2 << 4) | ||
| #define AT91_DDRSDRC_CAS_3 (3 << 4) | ||
| #define AT91_DDRSDRC_CAS_25 (6 << 4) | ||
| #define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */ | ||
| #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ | ||
|
|
||
| #define AT91_DDRSDRC_T0PR (AT91_DDRSDRC + 0x0C) /* Timing 0 Register */ | ||
| #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ | ||
| #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ | ||
| #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ | ||
| #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ | ||
| #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ | ||
| #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ | ||
| #define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */ | ||
| #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ | ||
|
|
||
| #define AT91_DDRSDRC_T1PR (AT91_DDRSDRC + 0x10) /* Timing 1 Register */ | ||
| #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ | ||
| #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ | ||
| #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ | ||
| #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ | ||
|
|
||
| #define AT91_DDRSDRC_LPR (AT91_DDRSDRC + 0x18) /* Low Power Register */ | ||
| #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ | ||
| #define AT91_DDRSDRC_LPCB_DISABLE 0 | ||
| #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 | ||
| #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | ||
| #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | ||
| #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | ||
| #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | ||
| #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | ||
| #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | ||
| #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ | ||
| #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) | ||
| #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) | ||
| #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) | ||
|
|
||
| #define AT91_DDRSDRC_MDR (AT91_DDRSDRC + 0x1C) /* Memory Device Register */ | ||
| #define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */ | ||
| #define AT91_DDRSDRC_MD_SDR 0 | ||
| #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | ||
| #define AT91_DDRSDRC_MD_DDR 2 | ||
| #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | ||
|
|
||
| #define AT91_DDRSDRC_DLLR (AT91_DDRSDRC + 0x20) /* DLL Information Register */ | ||
| #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ | ||
| #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ | ||
| #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ | ||
| #define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */ | ||
| #define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */ | ||
| #define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */ | ||
| #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ | ||
| #define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */ | ||
| #define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */ | ||
|
|
||
|
|
||
| #endif |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,73 @@ | ||
| /* | ||
| * include/asm-arm/arch-at91/at91sam9_smc.h | ||
| * | ||
| * Static Memory Controllers (SMC) - System peripherals registers. | ||
| * Based on AT91SAM9261 datasheet revision D. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| */ | ||
|
|
||
| #ifndef AT91SAM9_SMC_H | ||
| #define AT91SAM9_SMC_H | ||
|
|
||
| #define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ | ||
| #define AT91_SMC_NWESETUP_(x) ((x) << 0) | ||
| #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ | ||
| #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) | ||
| #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ | ||
| #define AT91_SMC_NRDSETUP_(x) ((x) << 16) | ||
| #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ | ||
| #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) | ||
|
|
||
| #define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ | ||
| #define AT91_SMC_NWEPULSE_(x) ((x) << 0) | ||
| #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ | ||
| #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) | ||
| #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ | ||
| #define AT91_SMC_NRDPULSE_(x) ((x) << 16) | ||
| #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ | ||
| #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) | ||
|
|
||
| #define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ | ||
| #define AT91_SMC_NWECYCLE_(x) ((x) << 0) | ||
| #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ | ||
| #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) | ||
|
|
||
| #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | ||
| #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | ||
| #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ | ||
| #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) | ||
| #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) | ||
| #define AT91_SMC_EXNWMODE_READY (3 << 4) | ||
| #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | ||
| #define AT91_SMC_BAT_SELECT (0 << 8) | ||
| #define AT91_SMC_BAT_WRITE (1 << 8) | ||
| #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ | ||
| #define AT91_SMC_DBW_8 (0 << 12) | ||
| #define AT91_SMC_DBW_16 (1 << 12) | ||
| #define AT91_SMC_DBW_32 (2 << 12) | ||
| #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ | ||
| #define AT91_SMC_TDF_(x) ((x) << 16) | ||
| #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ | ||
| #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ | ||
| #define AT91_SMC_PS (3 << 28) /* Page Size */ | ||
| #define AT91_SMC_PS_4 (0 << 28) | ||
| #define AT91_SMC_PS_8 (1 << 28) | ||
| #define AT91_SMC_PS_16 (2 << 28) | ||
| #define AT91_SMC_PS_32 (3 << 28) | ||
|
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||
| #if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ | ||
| #define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ | ||
| #define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ | ||
| #define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ | ||
| #define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | ||
| #endif | ||
|
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||
| #endif |