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yaml --- r: 228442 b: refs/heads/master c: 10cdc1a h: refs/heads/master v: v3
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Mike Frysinger
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Jan 10, 2011
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 73a400646b8e26615f3ef1a0a4bc0cd0d5bd284c | ||
| refs/heads/master: 10cdc1a78a02bb1d76b28b146083cb060399d86f |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,86 @@ | ||
| /* | ||
| * Copyright 2005-2010 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later. | ||
| */ | ||
|
|
||
| #ifndef _MACH_COMMON_PLL_H | ||
| #define _MACH_COMMON_PLL_H | ||
|
|
||
| #ifndef __ASSEMBLY__ | ||
|
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||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
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| #ifndef bfin_iwr_restore | ||
| static inline void | ||
| bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2) | ||
| { | ||
| #ifdef SIC_IWR | ||
| bfin_write_SIC_IWR(iwr0); | ||
| #else | ||
| bfin_write_SIC_IWR0(iwr0); | ||
| # ifdef SIC_IWR1 | ||
| bfin_write_SIC_IWR1(iwr1); | ||
| # endif | ||
| # ifdef SIC_IWR2 | ||
| bfin_write_SIC_IWR2(iwr2); | ||
| # endif | ||
| #endif | ||
| } | ||
| #endif | ||
|
|
||
| #ifndef bfin_iwr_save | ||
| static inline void | ||
| bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2, | ||
| unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2) | ||
| { | ||
| #ifdef SIC_IWR | ||
| *iwr0 = bfin_read_SIC_IWR(); | ||
| #else | ||
| *iwr0 = bfin_read_SIC_IWR0(); | ||
| # ifdef SIC_IWR1 | ||
| *iwr1 = bfin_read_SIC_IWR1(); | ||
| # endif | ||
| # ifdef SIC_IWR2 | ||
| *iwr2 = bfin_read_SIC_IWR2(); | ||
| # endif | ||
| #endif | ||
| bfin_iwr_restore(niwr0, niwr1, niwr2); | ||
| } | ||
| #endif | ||
|
|
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| static inline void _bfin_write_pll_relock(u32 addr, unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1, iwr2; | ||
|
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| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2); | ||
|
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| bfin_write16(addr, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_iwr_restore(iwr0, iwr1, iwr2); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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||
| /* Writing to PLL_CTL initiates a PLL relock sequence */ | ||
| static inline void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| _bfin_write_pll_relock(PLL_CTL, val); | ||
| } | ||
|
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||
| /* Writing to VR_CTL initiates a PLL relock sequence */ | ||
| static inline void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| _bfin_write_pll_relock(VR_CTL, val); | ||
| } | ||
|
|
||
| #endif | ||
|
|
||
| #endif |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,63 +1 @@ | ||
| /* | ||
| * Copyright 2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
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||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
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| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
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| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
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| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
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| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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||
| #endif /* _MACH_PLL_H */ | ||
| #include <mach-common/pll.h> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,63 +1 @@ | ||
| /* | ||
| * Copyright 2007-2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
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||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
||
| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
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| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
|
||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr0, iwr1; | ||
|
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| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
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||
| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr0 = bfin_read32(SIC_IWR0); | ||
| iwr1 = bfin_read32(SIC_IWR1); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR0, IWR_ENABLE(0)); | ||
| bfin_write32(SIC_IWR1, 0); | ||
|
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| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR0, iwr0); | ||
| bfin_write32(SIC_IWR1, iwr1); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
|
||
| #endif /* _MACH_PLL_H */ | ||
| #include <mach-common/pll.h> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,57 +1 @@ | ||
| /* | ||
| * Copyright 2005-2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
|
||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
|
||
| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
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| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR, iwr); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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||
| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
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| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
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| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR, iwr); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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||
| #endif /* _MACH_PLL_H */ | ||
| #include <mach-common/pll.h> |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,57 +1 @@ | ||
| /* | ||
| * Copyright 2005-2008 Analog Devices Inc. | ||
| * | ||
| * Licensed under the GPL-2 or later | ||
| */ | ||
|
|
||
| #ifndef _MACH_PLL_H | ||
| #define _MACH_PLL_H | ||
|
|
||
| #include <asm/blackfin.h> | ||
| #include <asm/irqflags.h> | ||
|
|
||
| /* Writing to PLL_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_PLL_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
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||
| if (val == bfin_read_PLL_CTL()) | ||
| return; | ||
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
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| bfin_write16(PLL_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR, iwr); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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| /* Writing to VR_CTL initiates a PLL relock sequence. */ | ||
| static __inline__ void bfin_write_VR_CTL(unsigned int val) | ||
| { | ||
| unsigned long flags, iwr; | ||
|
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| if (val == bfin_read_VR_CTL()) | ||
| return; | ||
|
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| flags = hard_local_irq_save(); | ||
| /* Enable the PLL Wakeup bit in SIC IWR */ | ||
| iwr = bfin_read32(SIC_IWR); | ||
| /* Only allow PPL Wakeup) */ | ||
| bfin_write32(SIC_IWR, IWR_ENABLE(0)); | ||
|
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| bfin_write16(VR_CTL, val); | ||
| SSYNC(); | ||
| asm("IDLE;"); | ||
|
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| bfin_write32(SIC_IWR, iwr); | ||
| hard_local_irq_restore(flags); | ||
| } | ||
|
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| #endif /* _MACH_PLL_H */ | ||
| #include <mach-common/pll.h> |
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