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mxc: TrustZone interrupt controller (TZIC) for Freescale i.MX5 family
Freescale i.MX51 processor uses a new interrupt controller. Add driver for TrustZone Interrupt Controller Signed-off-by: Amit Kucheria <amit.kucheria@canonical.com>
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| /* | ||
| * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| * | ||
| * The code contained herein is licensed under the GNU General Public | ||
| * License. You may obtain a copy of the GNU General Public License | ||
| * Version 2 or later at the following locations: | ||
| * | ||
| * http://www.opensource.org/licenses/gpl-license.html | ||
| * http://www.gnu.org/copyleft/gpl.html | ||
| */ | ||
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| #include <linux/module.h> | ||
| #include <linux/moduleparam.h> | ||
| #include <linux/init.h> | ||
| #include <linux/device.h> | ||
| #include <linux/errno.h> | ||
| #include <linux/io.h> | ||
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| #include <asm/mach/irq.h> | ||
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| #include <mach/hardware.h> | ||
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| /* | ||
| ***************************************** | ||
| * TZIC Registers * | ||
| ***************************************** | ||
| */ | ||
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| #define TZIC_INTCNTL 0x0000 /* Control register */ | ||
| #define TZIC_INTTYPE 0x0004 /* Controller Type register */ | ||
| #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ | ||
| #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ | ||
| #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ | ||
| #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ | ||
| #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ | ||
| #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ | ||
| #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ | ||
| #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ | ||
| #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ | ||
| #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ | ||
| #define TZIC_PND0 0x0D00 /* Pending Register 0 */ | ||
| #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ | ||
| #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ | ||
| #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ | ||
| #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ | ||
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| void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ | ||
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| /** | ||
| * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC | ||
| * | ||
| * @param irq interrupt source number | ||
| */ | ||
| static void tzic_mask_irq(unsigned int irq) | ||
| { | ||
| int index, off; | ||
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| index = irq >> 5; | ||
| off = irq & 0x1F; | ||
| __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); | ||
| } | ||
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| /** | ||
| * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC | ||
| * | ||
| * @param irq interrupt source number | ||
| */ | ||
| static void tzic_unmask_irq(unsigned int irq) | ||
| { | ||
| int index, off; | ||
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| index = irq >> 5; | ||
| off = irq & 0x1F; | ||
| __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); | ||
| } | ||
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| static unsigned int wakeup_intr[4]; | ||
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| /** | ||
| * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source. | ||
| * | ||
| * @param irq interrupt source number | ||
| * @param enable enable as wake-up if equal to non-zero | ||
| * disble as wake-up if equal to zero | ||
| * | ||
| * @return This function returns 0 on success. | ||
| */ | ||
| static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) | ||
| { | ||
| unsigned int index, off; | ||
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| index = irq >> 5; | ||
| off = irq & 0x1F; | ||
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| if (index > 3) | ||
| return -EINVAL; | ||
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| if (enable) | ||
| wakeup_intr[index] |= (1 << off); | ||
| else | ||
| wakeup_intr[index] &= ~(1 << off); | ||
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| return 0; | ||
| } | ||
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| static struct irq_chip mxc_tzic_chip = { | ||
| .name = "MXC_TZIC", | ||
| .ack = tzic_mask_irq, | ||
| .mask = tzic_mask_irq, | ||
| .unmask = tzic_unmask_irq, | ||
| .set_wake = tzic_set_wake_irq, | ||
| }; | ||
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| /* | ||
| * This function initializes the TZIC hardware and disables all the | ||
| * interrupts. It registers the interrupt enable and disable functions | ||
| * to the kernel for each interrupt source. | ||
| */ | ||
| void __init tzic_init_irq(void __iomem *irqbase) | ||
| { | ||
| int i; | ||
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| tzic_base = irqbase; | ||
| /* put the TZIC into the reset value with | ||
| * all interrupts disabled | ||
| */ | ||
| i = __raw_readl(tzic_base + TZIC_INTCNTL); | ||
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| __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); | ||
| __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); | ||
| __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); | ||
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| for (i = 0; i < 4; i++) | ||
| __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); | ||
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| /* disable all interrupts */ | ||
| for (i = 0; i < 4; i++) | ||
| __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); | ||
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| /* all IRQ no FIQ Warning :: No selection */ | ||
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| for (i = 0; i < MXC_INTERNAL_IRQS; i++) { | ||
| set_irq_chip(i, &mxc_tzic_chip); | ||
| set_irq_handler(i, handle_level_irq); | ||
| set_irq_flags(i, IRQF_VALID); | ||
| } | ||
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| pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); | ||
| } | ||
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| /** | ||
| * tzic_enable_wake() - enable wakeup interrupt | ||
| * | ||
| * @param is_idle 1 if called in idle loop (ENSET0 register); | ||
| * 0 to be used when called from low power entry | ||
| * @return 0 if successful; non-zero otherwise | ||
| */ | ||
| int tzic_enable_wake(int is_idle) | ||
| { | ||
| unsigned int i, v; | ||
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| __raw_writel(1, tzic_base + TZIC_DSMINT); | ||
| if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) | ||
| return -EAGAIN; | ||
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| for (i = 0; i < 4; i++) { | ||
| v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i]; | ||
| __raw_writel(v, TZIC_WAKEUP0(i)); | ||
| } | ||
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| return 0; | ||
| } |