---

yaml
---
r: 243654
b: refs/heads/master
c: ca44456
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 148086bb64694cc91624bab2a550d50f800eb4b7
+refs/heads/master: ca444564a947034557a85357b3911d067cac4b8f

trunk/Documentation/scheduler/sched-domains.txt

@@ -1,7 +1,8 @@
-Each CPU has a "base" scheduling domain (struct sched_domain). The domain
+Each CPU has a "base" scheduling domain (struct sched_domain). These are
+accessed via cpu_sched_domain(i) and this_sched_domain() macros. The domain
 hierarchy is built from these base domains via the ->parent pointer. ->parent
-MUST be NULL terminated, and domain structures should be per-CPU as they are
-locklessly updated.
+MUST be NULL terminated, and domain structures should be per-CPU as they
+are locklessly updated.
 
 Each scheduling domain spans a number of CPUs (stored in the ->span field).
 A domain's span MUST be a superset of it child's span (this restriction could
@@ -25,26 +26,11 @@ is treated as one entity. The load of a group is defined as the sum of the
 load of each of its member CPUs, and only when the load of a group becomes
 out of balance are tasks moved between groups.
 
-In kernel/sched.c, trigger_load_balance() is run periodically on each CPU
-through scheduler_tick(). It raises a softirq after the next regularly scheduled
-rebalancing event for the current runqueue has arrived. The actual load
-balancing workhorse, run_rebalance_domains()->rebalance_domains(), is then run
-in softirq context (SCHED_SOFTIRQ).
-
-The latter function takes two arguments: the current CPU and whether it was idle
-at the time the scheduler_tick() happened and iterates over all sched domains
-our CPU is on, starting from its base domain and going up the ->parent chain.
-While doing that, it checks to see if the current domain has exhausted its
-rebalance interval. If so, it runs load_balance() on that domain. It then checks
-the parent sched_domain (if it exists), and the parent of the parent and so
-forth.
-
-Initially, load_balance() finds the busiest group in the current sched domain.
-If it succeeds, it looks for the busiest runqueue of all the CPUs' runqueues in
-that group. If it manages to find such a runqueue, it locks both our initial
-CPU's runqueue and the newly found busiest one and starts moving tasks from it
-to our runqueue. The exact number of tasks amounts to an imbalance previously
-computed while iterating over this sched domain's groups.
+In kernel/sched.c, rebalance_tick is run periodically on each CPU. This
+function takes its CPU's base sched domain and checks to see if has reached
+its rebalance interval. If so, then it will run load_balance on that domain.
+rebalance_tick then checks the parent sched_domain (if it exists), and the
+parent of the parent and so forth.
 
 *** Implementing sched domains ***
 The "base" domain will "span" the first level of the hierarchy. In the case

trunk/Makefile

@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
-SUBLEVEL = 39
-EXTRAVERSION = -rc1
+SUBLEVEL = 38
+EXTRAVERSION =
 NAME = Flesh-Eating Bats with Fangs
 
 # *DOCUMENTATION*

trunk/arch/alpha/Kconfig

@@ -11,7 +11,7 @@ config ALPHA
 	select HAVE_GENERIC_HARDIRQS
 	select GENERIC_IRQ_PROBE
 	select AUTO_IRQ_AFFINITY if SMP
-	select GENERIC_IRQ_SHOW
+	select GENERIC_HARDIRQS_NO_DEPRECATED
 	help
 	  The Alpha is a 64-bit general-purpose processor designed and
 	  marketed by the Digital Equipment Corporation of blessed memory,

trunk/arch/alpha/kernel/irq.c

@@ -67,21 +67,68 @@ int irq_select_affinity(unsigned int irq)
 }
 #endif /* CONFIG_SMP */
 
-int arch_show_interrupts(struct seq_file *p, int prec)
+int
+show_interrupts(struct seq_file *p, void *v)
 {
 	int j;
+	int irq = *(loff_t *) v;
+	struct irqaction * action;
+	struct irq_desc *desc;
+	unsigned long flags;
 
 #ifdef CONFIG_SMP
-	seq_puts(p, "IPI: ");
-	for_each_online_cpu(j)
-		seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
-	seq_putc(p, '\n');
+	if (irq == 0) {
+		seq_puts(p, "           ");
+		for_each_online_cpu(j)
+			seq_printf(p, "CPU%d       ", j);
+		seq_putc(p, '\n');
+	}
+#endif
+
+	if (irq < ACTUAL_NR_IRQS) {
+		desc = irq_to_desc(irq);
+
+		if (!desc)
+			return 0;
+
+		raw_spin_lock_irqsave(&desc->lock, flags);
+		action = desc->action;
+		if (!action) 
+			goto unlock;
+		seq_printf(p, "%3d: ", irq);
+#ifndef CONFIG_SMP
+		seq_printf(p, "%10u ", kstat_irqs(irq));
+#else
+		for_each_online_cpu(j)
+			seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j));
 #endif
-	seq_puts(p, "PMI: ");
-	for_each_online_cpu(j)
-		seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
-	seq_puts(p, "          Performance Monitoring\n");
-	seq_printf(p, "ERR: %10lu\n", irq_err_count);
+		seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
+		seq_printf(p, "  %c%s",
+			(action->flags & IRQF_DISABLED)?'+':' ',
+			action->name);
+
+		for (action=action->next; action; action = action->next) {
+			seq_printf(p, ", %c%s",
+				  (action->flags & IRQF_DISABLED)?'+':' ',
+				   action->name);
+		}
+
+		seq_putc(p, '\n');
+unlock:
+		raw_spin_unlock_irqrestore(&desc->lock, flags);
+	} else if (irq == ACTUAL_NR_IRQS) {
+#ifdef CONFIG_SMP
+		seq_puts(p, "IPI: ");
+		for_each_online_cpu(j)
+			seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
+		seq_putc(p, '\n');
+#endif
+		seq_puts(p, "PMI: ");
+		for_each_online_cpu(j)
+			seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
+		seq_puts(p, "          Performance Monitoring\n");
+		seq_printf(p, "ERR: %10lu\n", irq_err_count);
+	}
 	return 0;
 }
 

trunk/arch/alpha/kernel/irq_alpha.c

@@ -228,7 +228,7 @@ struct irqaction timer_irqaction = {
 void __init
 init_rtc_irq(void)
 {
-	irq_set_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
+	set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
 				      handle_simple_irq, "RTC");
 	setup_irq(RTC_IRQ, &timer_irqaction);
 }

trunk/arch/alpha/kernel/irq_i8259.c

@@ -92,7 +92,7 @@ init_i8259a_irqs(void)
 	outb(0xff, 0xA1);	/* mask all of 8259A-2 */
 
 	for (i = 0; i < 16; i++) {
-		irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
 	}
 
 	setup_irq(2, &cascade);

trunk/arch/alpha/kernel/irq_pyxis.c

@@ -102,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
 	for (i = 16; i < 48; ++i) {
 		if ((ignore_mask >> i) & 1)
 			continue;
-		irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/irq_srm.c

@@ -51,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
 	for (i = 16; i < max; ++i) {
 		if (i < 64 && ((ignore_mask >> i) & 1))
 			continue;
-		irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 }

trunk/arch/alpha/kernel/sys_alcor.c

@@ -125,7 +125,7 @@ alcor_init_irq(void)
 		   on while IRQ probing.  */
 		if (i >= 16+20 && i <= 16+30)
 			continue;
-		irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 	i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;

trunk/arch/alpha/kernel/sys_cabriolet.c

@@ -105,8 +105,8 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
 		outb(0xff, 0x806);
 
 		for (i = 16; i < 35; ++i) {
-			irq_set_chip_and_handler(i, &cabriolet_irq_type,
-						 handle_level_irq);
+			set_irq_chip_and_handler(i, &cabriolet_irq_type,
+				handle_level_irq);
 			irq_set_status_flags(i, IRQ_LEVEL);
 		}
 	}

trunk/arch/alpha/kernel/sys_dp264.c

@@ -270,7 +270,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
 	long i;
 	for (i = imin; i <= imax; ++i) {
-		irq_set_chip_and_handler(i, ops, handle_level_irq);
+		set_irq_chip_and_handler(i, ops, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 }

trunk/arch/alpha/kernel/sys_eb64p.c

@@ -118,7 +118,7 @@ eb64p_init_irq(void)
 	init_i8259a_irqs();
 
 	for (i = 16; i < 32; ++i) {
-		irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_eiger.c

@@ -138,7 +138,7 @@ eiger_init_irq(void)
 	init_i8259a_irqs();
 
 	for (i = 16; i < 128; ++i) {
-		irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 }

trunk/arch/alpha/kernel/sys_jensen.c

@@ -171,11 +171,11 @@ jensen_init_irq(void)
 {
 	init_i8259a_irqs();
 
-	irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
-	irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
-	irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
-	irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
-	irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
+	set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
+	set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
+	set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
+	set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
+	set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
 
 	common_init_isa_dma();
 }

trunk/arch/alpha/kernel/sys_marvel.c

@@ -276,7 +276,7 @@ init_io7_irqs(struct io7 *io7,
 
 	/* Set up the lsi irqs.  */
 	for (i = 0; i < 128; ++i) {
-		irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
+		set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 
@@ -290,7 +290,7 @@ init_io7_irqs(struct io7 *io7,
 
 	/* Set up the msi irqs.  */
 	for (i = 128; i < (128 + 512); ++i) {
-		irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
+		set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 
@@ -308,8 +308,8 @@ marvel_init_irq(void)
 
 	/* Reserve the legacy irqs.  */
 	for (i = 0; i < 16; ++i) {
-		irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
+			handle_level_irq);
 	}
 
 	/* Init the io7 irqs.  */

trunk/arch/alpha/kernel/sys_mikasa.c

@@ -98,8 +98,7 @@ mikasa_init_irq(void)
 	mikasa_update_irq_hw(0);
 
 	for (i = 16; i < 32; ++i) {
-		irq_set_chip_and_handler(i, &mikasa_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_noritake.c

@@ -127,8 +127,7 @@ noritake_init_irq(void)
 	outw(0, 0x54c);
 
 	for (i = 16; i < 48; ++i) {
-		irq_set_chip_and_handler(i, &noritake_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_rawhide.c

@@ -180,8 +180,7 @@ rawhide_init_irq(void)
 	}
 
 	for (i = 16; i < 128; ++i) {
-		irq_set_chip_and_handler(i, &rawhide_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_rx164.c

@@ -99,7 +99,7 @@ rx164_init_irq(void)
 
 	rx164_update_irq_hw(0);
 	for (i = 16; i < 40; ++i) {
-		irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
+		set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_sable.c

@@ -518,8 +518,8 @@ sable_lynx_init_irq(int nr_of_irqs)
 	long i;
 
 	for (i = 0; i < nr_of_irqs; ++i) {
-		irq_set_chip_and_handler(i, &sable_lynx_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &sable_lynx_irq_type,
+			handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_takara.c

@@ -138,8 +138,7 @@ takara_init_irq(void)
 		takara_update_irq_hw(i, -1);
 
 	for (i = 16; i < 128; ++i) {
-		irq_set_chip_and_handler(i, &takara_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 

trunk/arch/alpha/kernel/sys_titan.c

@@ -179,7 +179,7 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
 	long i;
 	for (i = imin; i <= imax; ++i) {
-		irq_set_chip_and_handler(i, ops, handle_level_irq);
+		set_irq_chip_and_handler(i, ops, handle_level_irq);
 		irq_set_status_flags(i, IRQ_LEVEL);
 	}
 }

trunk/arch/alpha/kernel/sys_wildfire.c

@@ -183,17 +183,17 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
 	for (i = 0; i < 16; ++i) {
 		if (i == 2)
 			continue;
-		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
+			handle_level_irq);
 		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
 	}
 
-	irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
-				 handle_level_irq);
+	set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
+		handle_level_irq);
 	irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
 	for (i = 40; i < 64; ++i) {
-		irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
-					 handle_level_irq);
+		set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
+			handle_level_irq);
 		irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
 	}
 

trunk/arch/arm/Kconfig

@@ -28,7 +28,6 @@ config ARM
 	select HAVE_C_RECORDMCOUNT
 	select HAVE_GENERIC_HARDIRQS
 	select HAVE_SPARSE_IRQ
-	select GENERIC_IRQ_SHOW
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
@@ -366,7 +365,6 @@ config ARCH_MXC
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
 	select CLKDEV_LOOKUP
-	select HAVE_SCHED_CLOCK
 	help
 	  Support for Freescale MXC/iMX-based family of processors