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yaml
---
r: 331422
b: refs/heads/master
c: c986a3d
h: refs/heads/master
v: v3
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Greg Ungerer committed Sep 27, 2012
1 parent 139af4c commit a02b303
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Showing 12 changed files with 86 additions and 86 deletions.
2 changes: 1 addition & 1 deletion [refs]
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@@ -1,2 +1,2 @@
---
refs/heads/master: a45f56b272e59527e41d7fbfc9b49dac9b90644c
refs/heads/master: c986a3d520395604ca29a7fb9fca60a455abcc44
32 changes: 16 additions & 16 deletions trunk/arch/m68k/include/asm/m5206sim.h
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Expand Up @@ -21,23 +21,23 @@
/*
* Define the 5206 SIM register set addresses.
*/
#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
#ifdef CONFIG_M5206e
#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
#endif

#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
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24 changes: 12 additions & 12 deletions trunk/arch/m68k/include/asm/m5249sim.h
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Expand Up @@ -35,18 +35,18 @@
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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24 changes: 12 additions & 12 deletions trunk/arch/m68k/include/asm/m525xsim.h
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Expand Up @@ -33,18 +33,18 @@
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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8 changes: 4 additions & 4 deletions trunk/arch/m68k/include/asm/m5272sim.h
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Expand Up @@ -27,10 +27,10 @@
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */

#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */

#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
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24 changes: 12 additions & 12 deletions trunk/arch/m68k/include/asm/m5307sim.h
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Expand Up @@ -34,18 +34,18 @@
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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24 changes: 12 additions & 12 deletions trunk/arch/m68k/include/asm/m5407sim.h
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Expand Up @@ -34,18 +34,18 @@
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */

#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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4 changes: 2 additions & 2 deletions trunk/arch/m68k/platform/coldfire/device.c
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Expand Up @@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
{
#ifdef MCFUART_UIVR
/* UART0 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);

/* UART1 interrupt setup */
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
#endif
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20 changes: 10 additions & 10 deletions trunk/arch/m68k/platform/coldfire/intc-5272.c
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Expand Up @@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
u32 v;
irq -= MCFINT_VECBASE;
v = 0x8 << intc_irqmap[irq].index;
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
writel(v, intc_irqmap[irq].icr);
}
}

Expand All @@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
u32 v;
irq -= MCFINT_VECBASE;
v = 0xd << intc_irqmap[irq].index;
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
writel(v, intc_irqmap[irq].icr);
}
}

Expand All @@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(MCF_MBAR + intc_irqmap[irq].icr);
v = readl(intc_irqmap[irq].icr);
v &= (0x7 << intc_irqmap[irq].index);
v |= (0x8 << intc_irqmap[irq].index);
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
writel(v, intc_irqmap[irq].icr);
}
}
}
Expand All @@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
irq -= MCFINT_VECBASE;
if (intc_irqmap[irq].ack) {
u32 v;
v = readl(MCF_MBAR + MCFSIM_PITR);
v = readl(MCFSIM_PITR);
if (type == IRQ_TYPE_EDGE_FALLING)
v &= ~(0x1 << (32 - irq));
else
v |= (0x1 << (32 - irq));
writel(v, MCF_MBAR + MCFSIM_PITR);
writel(v, MCFSIM_PITR);
}
}
return 0;
Expand Down Expand Up @@ -163,10 +163,10 @@ void __init init_IRQ(void)
int irq, edge;

/* Mask all interrupt sources */
writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
writel(0x88888888, MCFSIM_ICR1);
writel(0x88888888, MCFSIM_ICR2);
writel(0x88888888, MCFSIM_ICR3);
writel(0x88888888, MCFSIM_ICR4);

for (irq = 0; (irq < NR_IRQS); irq++) {
irq_set_chip(irq, &intc_irq_chip);
Expand Down
2 changes: 1 addition & 1 deletion trunk/arch/m68k/platform/coldfire/m5249.c
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Expand Up @@ -57,7 +57,7 @@ static void __init m5249_qspi_init(void)
{
/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_QSPIICR);
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
}

Expand Down
4 changes: 2 additions & 2 deletions trunk/arch/m68k/platform/coldfire/m525x.c
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Expand Up @@ -30,7 +30,7 @@ static void __init m525x_qspi_init(void)

/* QSPI irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_QSPIICR);
MCFSIM_QSPIICR);
mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
}
Expand All @@ -42,7 +42,7 @@ static void __init m525x_i2c_init(void)

/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCF_MBAR + MCFSIM_I2CICR);
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);

/* second I2C controller is completely different */
Expand Down
4 changes: 2 additions & 2 deletions trunk/arch/m68k/platform/coldfire/timers.c
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Expand Up @@ -56,13 +56,13 @@ static void init_timer_irq(void)
#ifdef MCFSIM_ICR_AUTOVEC
/* Timer1 is always used as system timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER1ICR);
MCFSIM_TIMER1ICR);
mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);

#ifdef CONFIG_HIGHPROFILE
/* Timer2 is to be used as a high speed profile timer */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
MCF_MBAR + MCFSIM_TIMER2ICR);
MCFSIM_TIMER2ICR);
mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
#endif
#endif /* MCFSIM_ICR_AUTOVEC */
Expand Down

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