Skip to content

Commit

Permalink
---
Browse files Browse the repository at this point in the history
yaml
---
r: 325541
b: refs/heads/master
c: 7f98961
h: refs/heads/master
i:
  325539: e5acb77
v: v3
  • Loading branch information
H Hartley Sweeten authored and Greg Kroah-Hartman committed Sep 26, 2012
1 parent 2c8d066 commit a0dae3f
Show file tree
Hide file tree
Showing 2 changed files with 1 addition and 8 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 17553c88a21866333f4dfe15fe75591d80f02f76
refs/heads/master: 7f98961c0d4bdebc4508c59cead7f349e47feb7f
7 changes: 0 additions & 7 deletions trunk/drivers/staging/comedi/drivers/s626.c
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,6 @@ struct s626_private {
/* Pointer to logical adrs of DMA buffer used to hold DAC data. */
uint16_t Dacpol; /* Image of DAC polarity register. */
uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
uint16_t ChargeEnabled; /* Image of MISC2 Battery */
/* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
uint32_t I2CAdrs;
Expand Down Expand Up @@ -2667,12 +2666,6 @@ static void s626_initialize(struct comedi_device *dev)
for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
SetDAC(dev, chan, 0);

/* Init image of WRMISC2 Battery Charger Enabled control bit.
* This image is used when the state of the charger control bit,
* which has no direct hardware readback mechanism, is queried.
*/
devpriv->ChargeEnabled = 0;

/* Init image of watchdog timer interval in WRMISC2. This image
* maintains the value of the control bits of MISC2 are
* continuously reset to zero as long as the WD timer is disabled.
Expand Down

0 comments on commit a0dae3f

Please sign in to comment.