---

yaml
---
r: 247840
b: refs/heads/master
c: 0f8132b
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 567b99f84ea8efe979e020bd382dd735746b526b
+refs/heads/master: 0f8132b7431e241c29e61ac14f22549a6fca9632

trunk/drivers/video/via/hw.c

@@ -20,7 +20,6 @@
  */
 
 #include <linux/via-core.h>
-#include <asm/olpc.h>
 #include "global.h"
 
 static struct pll_config cle266_pll_config[] = {
@@ -876,10 +875,6 @@ void viafb_set_iga_path(void)
 				viaparinfo->chip_info->
 				lvds_chip_info2.output_interface);
 	}
-
-	/* looks like the OLPC has its display wired to DVP1 and LVDS2 */
-	if (machine_is_olpc())
-		viaparinfo->shared->iga2_devices = VIA_DVP1 | VIA_LVDS2;
 }
 
 static void set_color_register(u8 index, u8 red, u8 green, u8 blue)
@@ -1167,15 +1162,15 @@ void via_odev_to_seq(struct seq_file *m, u32 odev)
 
 static void load_fix_bit_crtc_reg(void)
 {
+	viafb_unlock_crt();
+
 	/* always set to 1 */
 	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
 	/* line compare should set all bits = 1 (extend modes) */
 	viafb_write_reg(CR18, VIACR, 0xff);
 	/* line compare should set all bits = 1 (extend modes) */
 	viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
 	/* line compare should set all bits = 1 (extend modes) */
-	viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
-	/* line compare should set all bits = 1 (extend modes) */
 	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
 	/* line compare should set all bits = 1 (extend modes) */
 	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
@@ -1186,6 +1181,10 @@ static void load_fix_bit_crtc_reg(void)
 	viafb_write_reg(CR08, VIACR, 0x00);
 	/* extend mode always set to 0h */
 	viafb_write_reg(CR14, VIACR, 0x00);
+	viafb_write_reg_mask(CR09, VIACR, 0x40, 0xDF);
+	viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
+
+	viafb_lock_crt();
 
 	/* If K8M800, enable Prefetch Mode. */
 	if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
@@ -2038,8 +2037,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
 	v_addr = crt_reg.ver_addr;
 	if (set_iga == IGA1) {
 		viafb_unlock_crt();
-		viafb_write_reg(CR09, VIACR, 0x00);	/*initial CR09=0 */
-		viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
 		viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
 	}
 
@@ -2052,7 +2049,6 @@ void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
 		break;
 	}
 
-	load_fix_bit_crtc_reg();
 	viafb_lock_crt();
 	viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
 	viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
@@ -2437,6 +2433,7 @@ int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp,
 		}
 	}
 
+	load_fix_bit_crtc_reg();
 	via_set_primary_pitch(viafbinfo->fix.line_length);
 	via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
 		: viafbinfo->fix.line_length);
@@ -2603,12 +2600,8 @@ int viafb_get_refresh(int hres, int vres, u32 long_refresh)
 			best = &vmode->crtc[i];
 	}
 
-	if (abs(best->refresh_rate - long_refresh) > 3) {
-		if (hres == 1200 && vres == 900)
-			return 49; /* OLPC DCON only supports 50 Hz */
-		else
-			return 60;
-	}
+	if (abs(best->refresh_rate - long_refresh) > 3)
+		return 60;
 
 	return best->refresh_rate;
 }

trunk/drivers/video/via/share.h

@@ -290,7 +290,6 @@
 #define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
 
 /* Definition Refresh Rate */
-#define REFRESH_49      49
 #define REFRESH_50      50
 #define REFRESH_60      60
 #define REFRESH_75      75

trunk/drivers/video/via/viamode.c

@@ -606,7 +606,7 @@ static struct crt_mode_table CRTM1200x720[] = {
 /* 1200x900 (DCON) */
 static struct crt_mode_table DCON1200x900[] = {
 	/* r_rate,               hsp,               vsp   */
-	{REFRESH_49, M1200X900_R60_HSP, M1200X900_R60_VSP,
+	{REFRESH_60, M1200X900_R60_HSP, M1200X900_R60_VSP,
 	/* The correct htotal is 1240, but this doesn't raster on VX855. */
 	/* Via suggested changing to a multiple of 16, hence 1264.       */
 	/*  HT,   HA,  HBS, HBE,  HSS, HSE,  VT,  VA, VBS, VBE, VSS, VSE */