---

yaml
---
r: 11628
b: refs/heads/master
c: ef1a128
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 529294d59fdc77bf15f00f2308bbeb73e03e7042
+refs/heads/master: ef1a12817aebc313049d226f96eee86e4bcc94a3

trunk/arch/ppc64/kernel/head.S

@@ -1556,20 +1556,17 @@ copy_to_here:
 	.section ".text";
 	.align 2 ;
 
-	.globl	pmac_secondary_start_1	
-pmac_secondary_start_1:	
-	li	r24, 1
-	b	.pmac_secondary_start
-
-	.globl pmac_secondary_start_2
-pmac_secondary_start_2:	
-	li	r24, 2
-	b	.pmac_secondary_start
-
-	.globl pmac_secondary_start_3
-pmac_secondary_start_3:
-	li	r24, 3
-	b	.pmac_secondary_start
+	.globl	__secondary_start_pmac_0
+__secondary_start_pmac_0:
+	/* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
+	li	r24,0
+	b	1f
+	li	r24,1
+	b	1f
+	li	r24,2
+	b	1f
+	li	r24,3
+1:
 
 _GLOBAL(pmac_secondary_start)
 	/* turn on 64-bit mode */

trunk/arch/ppc64/kernel/pmac_smp.c

@@ -59,9 +59,7 @@
 #define DBG(fmt...)
 #endif
 
-extern void pmac_secondary_start_1(void);
-extern void pmac_secondary_start_2(void);
-extern void pmac_secondary_start_3(void);
+extern void __secondary_start_pmac_0(void);
 
 extern struct smp_ops_t *smp_ops;
 
@@ -236,7 +234,7 @@ static int __init smp_core99_probe(void)
 
 static void __init smp_core99_kick_cpu(int nr)
 {
-	int save_vector, j;
+	unsigned int save_vector, j;
 	unsigned long new_vector;
 	unsigned long flags;
 	volatile unsigned int *vector
@@ -253,20 +251,9 @@ static void __init smp_core99_kick_cpu(int nr)
 	save_vector = *vector;
 
 	/* Setup fake reset vector that does	
-	 *   b .pmac_secondary_start - KERNELBASE
+	 *   b __secondary_start_pmac_0 + nr*8 - KERNELBASE
 	 */
-	switch(nr) {
-	case 1:
-		new_vector = (unsigned long)pmac_secondary_start_1;
-		break;
-	case 2:
-		new_vector = (unsigned long)pmac_secondary_start_2;
-		break;			
-	case 3:
-	default:
-		new_vector = (unsigned long)pmac_secondary_start_3;
-		break;
-	}
+	new_vector = (unsigned long) __secondary_start_pmac_0 + nr * 8;
 	*vector = 0x48000002 + (new_vector - KERNELBASE);
 
 	/* flush data cache and inval instruction cache */