Do the timer interrupt only once on CPU 0 ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
git-mirror · Oct 29, 2005 · a50b3e2 · a50b3e2
1 parent 8b200ce
commit a50b3e2
Showing 1 changed file with 9 additions and 8 deletions.
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
@@ -107,17 +107,18 @@ void sb1250_timer_interrupt(struct pt_regs *regs)
 	____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
 		       IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
 
-	/*
-	 * CPU 0 handles the global timer interrupt job
-	 */
 	if (cpu == 0) {
+		/*
+		 * CPU 0 handles the global timer interrupt job
+		 */
 		ll_timer_interrupt(irq, regs);
 	}
-
-	/*
-	 * every CPU should do profiling and process accouting
-	 */
-	ll_local_timer_interrupt(irq, regs);
+	else {
+		/*
+		 * other CPUs should just do profiling and process accounting
+		 */
+		ll_local_timer_interrupt(irq, regs);
+	}
 }
 
 /*