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yaml --- r: 329615 b: refs/heads/master c: af7afbd h: refs/heads/master i: 329613: 4186f7b 329611: 0ec2f6d 329607: 00bdba1 329599: 86f2f8f v: v3
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Ben Skeggs
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Oct 3, 2012
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,2 @@ | ||
| --- | ||
| refs/heads/master: 861d21074bbb141b0cc165a61c11f571571cda12 | ||
| refs/heads/master: af7afbd2e1409168698bde2f2846848b07d05d12 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,11 @@ | ||
| #ifndef __NV04_INSTMEM_H__ | ||
| #define __NV04_INSTMEM_H__ | ||
|
|
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| struct nv04_instmem_priv { | ||
| struct nouveau_gpuobj *vbios; | ||
| struct nouveau_gpuobj *ramht; | ||
| struct nouveau_gpuobj *ramro; | ||
| struct nouveau_gpuobj *ramfc; | ||
| }; | ||
|
|
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| #endif |
167 changes: 167 additions & 0 deletions
167
trunk/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,167 @@ | ||
| #include "drmP.h" | ||
| #include "drm.h" | ||
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| #include "nouveau_drv.h" | ||
| #include <engine/fifo.h> | ||
| #include <core/ramht.h> | ||
|
|
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| /* returns the size of fifo context */ | ||
| static int | ||
| nouveau_fifo_ctx_size(struct drm_device *dev) | ||
| { | ||
| return 128 * 32; | ||
| } | ||
|
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| int nv40_instmem_init(struct drm_device *dev) | ||
| { | ||
| struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
| struct nouveau_gpuobj *ramht = NULL; | ||
| u32 offset, length, vs, rsvd; | ||
| int ret; | ||
|
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| /* RAMIN always available */ | ||
| dev_priv->ramin_available = true; | ||
|
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| /* Reserve space at end of VRAM for PRAMIN */ | ||
| /* estimate grctx size, the magics come from nv40_grctx.c */ | ||
| vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8); | ||
| if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs; | ||
| else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs; | ||
| else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; | ||
| else rsvd = 0x4a40 * vs; | ||
| rsvd += 16 * 1024; | ||
| rsvd *= 32; /* per-channel */ | ||
|
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| rsvd += 512 * 1024; /* pci(e)gart table */ | ||
| rsvd += 512 * 1024; /* object storage */ | ||
|
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| dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096); | ||
|
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| /* Setup shared RAMHT */ | ||
| ret = nouveau_gpuobj_new_fake(dev, 0x10000, ~0, 4096, | ||
| NVOBJ_FLAG_ZERO_ALLOC, &ramht); | ||
| if (ret) | ||
| return ret; | ||
|
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| ret = nouveau_ramht_new(dev, ramht, &dev_priv->ramht); | ||
| nouveau_gpuobj_ref(NULL, &ramht); | ||
| if (ret) | ||
| return ret; | ||
|
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| /* And RAMRO */ | ||
| ret = nouveau_gpuobj_new_fake(dev, 0x11200, ~0, 512, | ||
| NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramro); | ||
| if (ret) | ||
| return ret; | ||
|
|
||
| /* And RAMFC */ | ||
| length = nouveau_fifo_ctx_size(dev); | ||
| offset = 0x20000; | ||
|
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| ret = nouveau_gpuobj_new_fake(dev, offset, ~0, length, | ||
| NVOBJ_FLAG_ZERO_ALLOC, &dev_priv->ramfc); | ||
| if (ret) | ||
| return ret; | ||
|
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| /* Only allow space after RAMFC to be used for object allocation */ | ||
| offset += length; | ||
|
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| /* It appears RAMRO (or something?) is controlled by 0x2220/0x2230 | ||
| * on certain NV4x chipsets as well as RAMFC. When 0x2230 == 0 | ||
| * ("new style" control) the upper 16-bits of 0x2220 points at this | ||
| * other mysterious table that's clobbering important things. | ||
| * | ||
| * We're now pointing this at RAMIN+0x30000 to avoid RAMFC getting | ||
| * smashed to pieces on us, so reserve 0x30000-0x40000 too.. | ||
| */ | ||
| if (offset < 0x40000) | ||
| offset = 0x40000; | ||
|
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| ret = drm_mm_init(&dev_priv->ramin_heap, offset, | ||
| dev_priv->ramin_rsvd_vram - offset); | ||
| if (ret) { | ||
| NV_ERROR(dev, "Failed to init RAMIN heap: %d\n", ret); | ||
| return ret; | ||
| } | ||
|
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| return 0; | ||
| } | ||
|
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| void | ||
| nv40_instmem_takedown(struct drm_device *dev) | ||
| { | ||
| struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
|
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| nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL); | ||
| nouveau_gpuobj_ref(NULL, &dev_priv->ramro); | ||
| nouveau_gpuobj_ref(NULL, &dev_priv->ramfc); | ||
|
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| if (drm_mm_initialized(&dev_priv->ramin_heap)) | ||
| drm_mm_takedown(&dev_priv->ramin_heap); | ||
| } | ||
|
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| int | ||
| nv40_instmem_suspend(struct drm_device *dev) | ||
| { | ||
| return 0; | ||
| } | ||
|
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| void | ||
| nv40_instmem_resume(struct drm_device *dev) | ||
| { | ||
| } | ||
|
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| int | ||
| nv40_instmem_get(struct nouveau_gpuobj *gpuobj, struct nouveau_channel *chan, | ||
| u32 size, u32 align) | ||
| { | ||
| struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; | ||
| struct drm_mm_node *ramin = NULL; | ||
|
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| do { | ||
| if (drm_mm_pre_get(&dev_priv->ramin_heap)) | ||
| return -ENOMEM; | ||
|
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| spin_lock(&dev_priv->ramin_lock); | ||
| ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0); | ||
| if (ramin == NULL) { | ||
| spin_unlock(&dev_priv->ramin_lock); | ||
| return -ENOMEM; | ||
| } | ||
|
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| ramin = drm_mm_get_block_atomic(ramin, size, align); | ||
| spin_unlock(&dev_priv->ramin_lock); | ||
| } while (ramin == NULL); | ||
|
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| gpuobj->node = ramin; | ||
| gpuobj->vinst = ramin->start; | ||
| return 0; | ||
| } | ||
|
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| void | ||
| nv40_instmem_put(struct nouveau_gpuobj *gpuobj) | ||
| { | ||
| struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; | ||
|
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| spin_lock(&dev_priv->ramin_lock); | ||
| drm_mm_put_block(gpuobj->node); | ||
| gpuobj->node = NULL; | ||
| spin_unlock(&dev_priv->ramin_lock); | ||
| } | ||
|
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| int | ||
| nv40_instmem_map(struct nouveau_gpuobj *gpuobj) | ||
| { | ||
| gpuobj->pinst = gpuobj->vinst; | ||
| return 0; | ||
| } | ||
|
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| void | ||
| nv40_instmem_unmap(struct nouveau_gpuobj *gpuobj) | ||
| { | ||
| } | ||
|
|
||
| void | ||
| nv40_instmem_flush(struct drm_device *dev) | ||
| { | ||
| } |
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