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yaml
---
r: 318531
b: refs/heads/master
c: 9d9740f
h: refs/heads/master
i:
  318529: d71503c
  318527: 039459a
v: v3
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Paulo Zanoni authored and Daniel Vetter committed May 30, 2012
1 parent bd0dc65 commit a64a504
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Showing 2 changed files with 28 additions and 1 deletion.
2 changes: 1 addition & 1 deletion [refs]
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: c30b61109021ecbc81966573862cf98f655e3531
refs/heads/master: 9d9740f099f2eaf309c4c9cbc0d732507140db28
27 changes: 27 additions & 0 deletions trunk/drivers/gpu/drm/i915/intel_hdmi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -133,16 +133,19 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,

I915_WRITE(VIDEO_DIP_CTL, val);

mmiowb();
for (i = 0; i < len; i += 4) {
I915_WRITE(VIDEO_DIP_DATA, *data);
data++;
}
mmiowb();

val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC;

I915_WRITE(VIDEO_DIP_CTL, val);
POSTING_READ(VIDEO_DIP_CTL);
}

static void ibx_write_infoframe(struct drm_encoder *encoder,
Expand All @@ -165,16 +168,19 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,

I915_WRITE(reg, val);

mmiowb();
for (i = 0; i < len; i += 4) {
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
data++;
}
mmiowb();

val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC;

I915_WRITE(reg, val);
POSTING_READ(reg);
}

static void cpt_write_infoframe(struct drm_encoder *encoder,
Expand All @@ -200,16 +206,19 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,

I915_WRITE(reg, val);

mmiowb();
for (i = 0; i < len; i += 4) {
I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
data++;
}
mmiowb();

val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC;

I915_WRITE(reg, val);
POSTING_READ(reg);
}

static void vlv_write_infoframe(struct drm_encoder *encoder,
Expand All @@ -232,16 +241,19 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,

I915_WRITE(reg, val);

mmiowb();
for (i = 0; i < len; i += 4) {
I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
data++;
}
mmiowb();

val |= g4x_infoframe_enable(frame);
val &= ~VIDEO_DIP_FREQ_MASK;
val |= VIDEO_DIP_FREQ_VSYNC;

I915_WRITE(reg, val);
POSTING_READ(reg);
}

static void hsw_write_infoframe(struct drm_encoder *encoder,
Expand All @@ -262,13 +274,16 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
val &= ~hsw_infoframe_enable(frame);
I915_WRITE(ctl_reg, val);

mmiowb();
for (i = 0; i < len; i += 4) {
I915_WRITE(data_reg + i, *data);
data++;
}
mmiowb();

val |= hsw_infoframe_enable(frame);
I915_WRITE(ctl_reg, val);
POSTING_READ(ctl_reg);
}

static void intel_set_infoframe(struct drm_encoder *encoder,
Expand Down Expand Up @@ -335,6 +350,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
return;
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
POSTING_READ(reg);
return;
}

Expand All @@ -353,6 +369,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
if (val & VIDEO_DIP_ENABLE) {
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
POSTING_READ(reg);
}
val &= ~VIDEO_DIP_PORT_MASK;
val |= port;
Expand All @@ -362,6 +379,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
val &= ~VIDEO_DIP_ENABLE_VENDOR;

I915_WRITE(reg, val);
POSTING_READ(reg);

intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);
Expand All @@ -385,6 +403,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
return;
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
POSTING_READ(reg);
return;
}

Expand All @@ -406,6 +425,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
if (val & VIDEO_DIP_ENABLE) {
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
POSTING_READ(reg);
}
val &= ~VIDEO_DIP_PORT_MASK;
val |= port;
Expand All @@ -416,6 +436,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
VIDEO_DIP_ENABLE_GCP);

I915_WRITE(reg, val);
POSTING_READ(reg);

intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);
Expand All @@ -438,6 +459,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
return;
val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
I915_WRITE(reg, val);
POSTING_READ(reg);
return;
}

Expand All @@ -447,6 +469,7 @@ static void cpt_set_infoframes(struct drm_encoder *encoder,
VIDEO_DIP_ENABLE_GCP);

I915_WRITE(reg, val);
POSTING_READ(reg);

intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);
Expand All @@ -469,6 +492,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
return;
val &= ~VIDEO_DIP_ENABLE;
I915_WRITE(reg, val);
POSTING_READ(reg);
return;
}

Expand All @@ -477,6 +501,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder,
VIDEO_DIP_ENABLE_GCP);

I915_WRITE(reg, val);
POSTING_READ(reg);

intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);
Expand All @@ -493,13 +518,15 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,

if (!intel_hdmi->has_hdmi_sink) {
I915_WRITE(reg, 0);
POSTING_READ(reg);
return;
}

val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);

I915_WRITE(reg, val);
POSTING_READ(reg);

intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
intel_hdmi_set_spd_infoframe(encoder);
Expand Down

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