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Arnd Bergmann
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trunk/Documentation/devicetree/bindings/arm/vexpress.txt
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| ARM Versatile Express boards family | ||
| ----------------------------------- | ||
|
|
||
| ARM's Versatile Express platform consists of a motherboard and one | ||
| or more daughterboards (tiles). The motherboard provides a set of | ||
| peripherals. Processor and RAM "live" on the tiles. | ||
|
|
||
| The motherboard and each core tile should be described by a separate | ||
| Device Tree source file, with the tile's description including | ||
| the motherboard file using a /include/ directive. As the motherboard | ||
| can be initialized in one of two different configurations ("memory | ||
| maps"), care must be taken to include the correct one. | ||
|
|
||
| Required properties in the root node: | ||
| - compatible value: | ||
| compatible = "arm,vexpress,<model>", "arm,vexpress"; | ||
| where <model> is the full tile model name (as used in the tile's | ||
| Technical Reference Manual), eg.: | ||
| - for Coretile Express A5x2 (V2P-CA5s): | ||
| compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; | ||
| - for Coretile Express A9x4 (V2P-CA9): | ||
| compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; | ||
| If a tile comes in several variants or can be used in more then one | ||
| configuration, the compatible value should be: | ||
| compatible = "arm,vexpress,<model>,<variant>", \ | ||
| "arm,vexpress,<model>", "arm,vexpress"; | ||
| eg: | ||
| - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: | ||
| compatible = "arm,vexpress,v2p-ca15,tc1", \ | ||
| "arm,vexpress,v2p-ca15", "arm,vexpress"; | ||
| - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: | ||
| compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ | ||
| "arm,vexpress,v2f-2xv6", "arm,vexpress"; | ||
|
|
||
| Optional properties in the root node: | ||
| - tile model name (use name from the tile's Technical Reference | ||
| Manual, eg. "V2P-CA5s") | ||
| model = "<model>"; | ||
| - tile's HBI number (unique ARM's board model ID, visible on the | ||
| PCB's silkscreen) in hexadecimal transcription: | ||
| arm,hbi = <0xhbi> | ||
| eg: | ||
| - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: | ||
| arm,hbi = <0x191>; | ||
| - Coretile Express A9x4 (V2P-CA9) HBI-0225: | ||
| arm,hbi = <0x225>; | ||
|
|
||
| Top-level standard "cpus" node is required. It must contain a node | ||
| with device_type = "cpu" property for every available core, eg.: | ||
|
|
||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
|
||
| cpu@0 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a5"; | ||
| reg = <0>; | ||
| }; | ||
| }; | ||
|
|
||
| The motherboard description file provides a single "motherboard" node | ||
| using 2 address cells corresponding to the Static Memory Bus used | ||
| between the motherboard and the tile. The first cell defines the Chip | ||
| Select (CS) line number, the second cell address offset within the CS. | ||
| All interrupt lines between the motherboard and the tile are active | ||
| high and are described using single cell. | ||
|
|
||
| Optional properties of the "motherboard" node: | ||
| - motherboard's memory map variant: | ||
| arm,v2m-memory-map = "<name>"; | ||
| where name is one of: | ||
| - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also | ||
| referred to as "ARM Cortex-A Series memory map": | ||
| arm,v2m-memory-map = "rs1"; | ||
| When this property is missing, the motherboard is using the original | ||
| memory map (also known as the "Legacy memory map", primarily used | ||
| with the original CoreTile Express A9x4) with peripherals on CS7. | ||
|
|
||
| Motherboard .dtsi files provide a set of labelled peripherals that | ||
| can be used to obtain required phandle in the tile's "aliases" node: | ||
| - UARTs, note that the numbers correspond to the physical connectors | ||
| on the motherboard's back panel: | ||
| v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 | ||
| - I2C controllers: | ||
| v2m_i2c_dvi and v2m_i2c_pcie | ||
| - SP804 timers: | ||
| v2m_timer01 and v2m_timer23 | ||
|
|
||
| Current Linux implementation requires a "arm,v2m_timer" alias | ||
| pointing at one of the motherboard's SP804 timers, if it is to be | ||
| used as the system timer. This alias should be defined in the | ||
| motherboard files. | ||
|
|
||
| The tile description must define "ranges", "interrupt-map-mask" and | ||
| "interrupt-map" properties to translate the motherboard's address | ||
| and interrupt space into one used by the tile's processor. | ||
|
|
||
| Abbreviated example: | ||
|
|
||
| /dts-v1/; | ||
|
|
||
| / { | ||
| model = "V2P-CA5s"; | ||
| arm,hbi = <0x225>; | ||
| compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; | ||
| interrupt-parent = <&gic>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
|
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||
| chosen { }; | ||
|
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||
| aliases { | ||
| serial0 = &v2m_serial0; | ||
| }; | ||
|
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||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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||
| cpu@0 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a5"; | ||
| reg = <0>; | ||
| }; | ||
| }; | ||
|
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||
| gic: interrupt-controller@2c001000 { | ||
| compatible = "arm,cortex-a9-gic"; | ||
| #interrupt-cells = <3>; | ||
| #address-cells = <0>; | ||
| interrupt-controller; | ||
| reg = <0x2c001000 0x1000>, | ||
| <0x2c000100 0x100>; | ||
| }; | ||
|
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||
| motherboard { | ||
| /* CS0 is visible at 0x08000000 */ | ||
| ranges = <0 0 0x08000000 0x04000000>; | ||
| interrupt-map-mask = <0 0 63>; | ||
| /* Active high IRQ 0 is connected to GIC's SPI0 */ | ||
| interrupt-map = <0 0 0 &gic 0 0 4>; | ||
| }; | ||
| }; | ||
|
|
||
| /include/ "vexpress-v2m-rs1.dtsi" |
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