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yaml
---
r: 210113
b: refs/heads/master
c: 3297c2e
h: refs/heads/master
i:
  210111: 9551e73
v: v3
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Jongpill Lee authored and Kukjin Kim committed Aug 27, 2010
1 parent b1c83ee commit a69a741
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Showing 3 changed files with 16 additions and 9 deletions.
2 changes: 1 addition & 1 deletion [refs]
Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
---
refs/heads/master: 5a847b4af8057f0297356824f793988d311d7aa0
refs/heads/master: 3297c2e6d7c3b1498b28c93141056cbe96444fde
21 changes: 13 additions & 8 deletions trunk/arch/arm/mach-s5pv310/clock.c
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,11 @@ static struct clk clk_sclk_hdmi27m = {
.rate = 27000000,
};

static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
}

static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
Expand Down Expand Up @@ -397,7 +402,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 0,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &clkset_group,
Expand All @@ -407,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 1,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
Expand All @@ -417,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 2,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
Expand All @@ -427,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "uclk1",
.id = 3,
.enable = s5pv310_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
Expand All @@ -437,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
.clk = {
.name = "sclk_pwm",
.id = -1,
.enable = s5pv310_clk_ip_peril_ctrl,
.enable = s5pv310_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &clkset_group,
Expand Down
2 changes: 2 additions & 0 deletions trunk/arch/arm/mach-s5pv310/include/mach/regs-clock.h
Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,8 @@
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)

#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)

#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)

#define S5P_CLKSRC_CORE S5P_CLKREG(0x10200)
Expand Down

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