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staging: ti dspbridge: Rename words with camel case.
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The intention of this patch is to rename the remaining variables with camel
case. Variables will be renamed avoiding camel case and Hungarian notation.
The words to be renamed in this patch are:
========================================
aAddr to addrs
aArgs to args
aSize to len
baseAddress to base_address
bDynamicLoad to dynamic_load
bForce to force
cCharSize to char_size
cContentSize to content_size
cCount to count
cDspCharSize to dsp_char_size
cIndex to index
ClkId to clock_id
cOrigin to origin
dataBasePhys to data_base_phys
dcdObjUnion to dcd_obj
deviceContext to device_ctxt
========================================

Signed-off-by: Rene Sapiens <rene.sapiens@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Rene Sapiens authored and Greg Kroah-Hartman committed Jul 8, 2010
1 parent 8dd1260 commit a6bff48
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Showing 16 changed files with 185 additions and 185 deletions.
2 changes: 1 addition & 1 deletion drivers/staging/tidspbridge/core/_tiomap_pwr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,6 @@ int handle_constraints_set(struct bridge_dev_context *dev_context,
* This function sets the group selction bits for while
* enabling/disabling.
*/
void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable);
void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable);

#endif /* _TIOMAP_PWR_ */
4 changes: 2 additions & 2 deletions drivers/staging/tidspbridge/core/tiomap3430_pwr.c
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Original file line number Diff line number Diff line change
Expand Up @@ -407,7 +407,7 @@ int post_scale_dsp(struct bridge_dev_context *dev_context,
return status;
}

void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable)
void dsp_clk_wakeup_event_ctrl(u32 clock_id, bool enable)
{
struct cfg_hostres *resources;
int status = 0;
Expand All @@ -428,7 +428,7 @@ void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable)
if (!resources)
return;

switch (ClkId) {
switch (clock_id) {
case BPWR_GP_TIMER5:
iva2_grpsel = (u32) *((reg_uword32 *)
((u32) (resources->dw_per_pm_base) +
Expand Down
8 changes: 4 additions & 4 deletions drivers/staging/tidspbridge/core/tiomap_io.c
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Original file line number Diff line number Diff line change
Expand Up @@ -227,7 +227,7 @@ int write_dsp_data(struct bridge_dev_context *hDevContext,
int write_ext_dsp_data(struct bridge_dev_context *dev_context,
IN u8 *pbHostBuf, u32 dwDSPAddr,
u32 ul_num_bytes, u32 ulMemType,
bool bDynamicLoad)
bool dynamic_load)
{
u32 dw_base_addr = dev_context->dw_dsp_ext_base_addr;
u32 dw_offset = 0;
Expand Down Expand Up @@ -259,7 +259,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
}

/* If dynamic, force remap/unmap */
if ((bDynamicLoad || trace_load) && dw_base_addr) {
if ((dynamic_load || trace_load) && dw_base_addr) {
dw_base_addr = 0;
MEM_UNMAP_LINEAR_ADDRESS((void *)
dev_context->dw_dsp_ext_base_addr);
Expand All @@ -271,7 +271,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
ret = dev_get_symbol(dev_context->hdev_obj,
SHMBASENAME, &ul_shm_base_virt);
DBC_ASSERT(ul_shm_base_virt != 0);
if (bDynamicLoad) {
if (dynamic_load) {
if (DSP_SUCCEEDED(ret)) {
if (symbols_reloaded)
ret =
Expand Down Expand Up @@ -377,7 +377,7 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
*((u32 *) pbHostBuf) = dw_base_addr + dw_offset;
}
/* Unmap here to force remap for other Ext loads */
if ((bDynamicLoad || trace_load) && dev_context->dw_dsp_ext_base_addr) {
if ((dynamic_load || trace_load) && dev_context->dw_dsp_ext_base_addr) {
MEM_UNMAP_LINEAR_ADDRESS((void *)
dev_context->dw_dsp_ext_base_addr);
dev_context->dw_dsp_ext_base_addr = 0x0;
Expand Down
2 changes: 1 addition & 1 deletion drivers/staging/tidspbridge/core/tiomap_io.h
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ extern int write_dsp_data(struct bridge_dev_context *dev_context,
extern int write_ext_dsp_data(struct bridge_dev_context *dev_context,
IN u8 *pbHostBuf, u32 dwDSPAddr,
u32 ul_num_bytes, u32 ulMemType,
bool bDynamicLoad);
bool dynamic_load);

/*
* ======== write_ext32_bit_dsp_data ========
Expand Down
108 changes: 54 additions & 54 deletions drivers/staging/tidspbridge/hw/MMURegAcM.h
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Original file line number Diff line number Diff line change
Expand Up @@ -25,158 +25,158 @@

#if defined(USE_LEVEL_1_MACROS)

#define MMUMMU_SYSCONFIG_READ_REGISTER32(baseAddress)\
#define MMUMMU_SYSCONFIG_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_READ_REGISTER32),\
__raw_readl((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET))
__raw_readl((base_address)+MMU_MMU_SYSCONFIG_OFFSET))

#define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(baseAddress, value)\
#define MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_IDLE_MODE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_IDLE_MODE_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_IDLE_MODE_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_IDLE_MODE_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(baseAddress, value)\
#define MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_SYSCONFIG_AUTO_IDLE_WRITE32);\
data &= ~(MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_AUTO_IDLE_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_AUTO_IDLE_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_IRQSTATUS_READ_REGISTER32(baseAddress)\
#define MMUMMU_IRQSTATUS_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\
__raw_readl((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET))
__raw_readl((base_address)+MMU_MMU_IRQSTATUS_OFFSET))

#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_IRQSTATUS_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQSTATUS_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_IRQENABLE_READ_REGISTER32(baseAddress)\
#define MMUMMU_IRQENABLE_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_READ_REGISTER32),\
__raw_readl((baseAddress)+MMU_MMU_IRQENABLE_OFFSET))
__raw_readl((base_address)+MMU_MMU_IRQENABLE_OFFSET))

#define MMUMMU_IRQENABLE_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_IRQENABLE_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_IRQENABLE_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_WALKING_STTWL_RUNNING_READ32(baseAddress)\
#define MMUMMU_WALKING_STTWL_RUNNING_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_WALKING_STTWL_RUNNING_READ32),\
(((__raw_readl(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\
(((__raw_readl(((base_address)+(MMU_MMU_WALKING_ST_OFFSET))))\
& MMU_MMU_WALKING_ST_TWL_RUNNING_MASK) >>\
MMU_MMU_WALKING_ST_TWL_RUNNING_OFFSET))

#define MMUMMU_CNTLTWL_ENABLE_READ32(baseAddress)\
#define MMUMMU_CNTLTWL_ENABLE_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_READ32),\
(((__raw_readl(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\
(((__raw_readl(((base_address)+(MMU_MMU_CNTL_OFFSET)))) &\
MMU_MMU_CNTL_TWL_ENABLE_MASK) >>\
MMU_MMU_CNTL_TWL_ENABLE_OFFSET))

#define MMUMMU_CNTLTWL_ENABLE_WRITE32(baseAddress, value)\
#define MMUMMU_CNTLTWL_ENABLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLTWL_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_TWL_ENABLE_MASK);\
newValue <<= MMU_MMU_CNTL_TWL_ENABLE_OFFSET;\
newValue &= MMU_MMU_CNTL_TWL_ENABLE_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_CNTLMMU_ENABLE_WRITE32(baseAddress, value)\
#define MMUMMU_CNTLMMU_ENABLE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CNTLMMU_ENABLE_WRITE32);\
data &= ~(MMU_MMU_CNTL_MMU_ENABLE_MASK);\
newValue <<= MMU_MMU_CNTL_MMU_ENABLE_OFFSET;\
newValue &= MMU_MMU_CNTL_MMU_ENABLE_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_FAULT_AD_READ_REGISTER32(baseAddress)\
#define MMUMMU_FAULT_AD_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FAULT_AD_READ_REGISTER32),\
__raw_readl((baseAddress)+MMU_MMU_FAULT_AD_OFFSET))
__raw_readl((base_address)+MMU_MMU_FAULT_AD_OFFSET))

#define MMUMMU_TTB_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_TTB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_TTB_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_TTB_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_LOCK_READ_REGISTER32(baseAddress)\
#define MMUMMU_LOCK_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_READ_REGISTER32),\
__raw_readl((baseAddress)+MMU_MMU_LOCK_OFFSET))
__raw_readl((base_address)+MMU_MMU_LOCK_OFFSET))

#define MMUMMU_LOCK_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_LOCK_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_LOCK_BASE_VALUE_READ32(baseAddress)\
#define MMUMMU_LOCK_BASE_VALUE_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_BASE_VALUE_READ32),\
(((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_BASE_VALUE_MASK) >>\
MMU_MMU_LOCK_BASE_VALUE_OFFSET))

#define MMUMMU_LOCK_BASE_VALUE_WRITE32(baseAddress, value)\
#define MMUMMU_LOCK_BASE_VALUE_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\
data &= ~(MMU_MMU_LOCK_BASE_VALUE_MASK);\
newValue <<= MMU_MMU_LOCK_BASE_VALUE_OFFSET;\
newValue &= MMU_MMU_LOCK_BASE_VALUE_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(baseAddress)\
#define MMUMMU_LOCK_CURRENT_VICTIM_READ32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_READ32),\
(((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
(((__raw_readl(((base_address)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_CURRENT_VICTIM_MASK) >>\
MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET))

#define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(baseAddress, value)\
#define MMUMMU_LOCK_CURRENT_VICTIM_WRITE32(base_address, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 data = __raw_readl((baseAddress)+offset);\
register u32 data = __raw_readl((base_address)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LOCK_CURRENT_VICTIM_WRITE32);\
data &= ~(MMU_MMU_LOCK_CURRENT_VICTIM_MASK);\
newValue <<= MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET;\
newValue &= MMU_MMU_LOCK_CURRENT_VICTIM_MASK;\
newValue |= data;\
__raw_writel(newValue, baseAddress+offset);\
__raw_writel(newValue, base_address+offset);\
}

#define MMUMMU_LOCK_CURRENT_VICTIM_SET32(var, value)\
Expand All @@ -185,40 +185,40 @@
(((value) << MMU_MMU_LOCK_CURRENT_VICTIM_OFFSET) &\
MMU_MMU_LOCK_CURRENT_VICTIM_MASK)))

#define MMUMMU_LD_TLB_READ_REGISTER32(baseAddress)\
#define MMUMMU_LD_TLB_READ_REGISTER32(base_address)\
(_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_READ_REGISTER32),\
__raw_readl((baseAddress)+MMU_MMU_LD_TLB_OFFSET))
__raw_readl((base_address)+MMU_MMU_LD_TLB_OFFSET))

#define MMUMMU_LD_TLB_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_LD_TLB_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_LD_TLB_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_CAM_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_CAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_CAM_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_CAM_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_RAM_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_RAM_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_RAM_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_RAM_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(baseAddress, value)\
#define MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32(base_address, value)\
{\
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL1_EASI(EASIL1_MMUMMU_FLUSH_ENTRY_WRITE_REGISTER32);\
__raw_writel(newValue, (baseAddress)+offset);\
__raw_writel(newValue, (base_address)+offset);\
}

#endif /* USE_LEVEL_1_MACROS */
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