---

yaml
---
r: 297538
b: refs/heads/master
c: 833bc03
h: refs/heads/master
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 359291a1a095a8a402405cd9c4bab46684e7bcfe
+refs/heads/master: 833bc03bf14ef6d3f82d86845c29aa1f7e2037e3

trunk/drivers/dma/imx-dma.c

@@ -129,7 +129,6 @@ enum  imxdma_prep_type {
  */
 
 struct imxdma_channel_internal {
-	struct scatterlist *sg;
 	unsigned int resbytes;
 
 	int in_use;
@@ -278,11 +277,11 @@ static void imxdma_enable_hw(struct imxdma_desc *d)
 		CCR_ACRPT, DMA_CCR(channel));
 
 	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdmac->internal.sg && imxdma_hw_chain(&imxdmac->internal)) {
-		imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
-		if (imxdmac->internal.sg) {
+			d->sg && imxdma_hw_chain(&imxdmac->internal)) {
+		d->sg = sg_next(d->sg);
+		if (d->sg) {
 			u32 tmp;
-			imxdma_sg_next(d, imxdmac->internal.sg);
+			imxdma_sg_next(d, d->sg);
 			tmp = imx_dmav1_readl(DMA_CCR(channel));
 			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
 				DMA_CCR(channel));
@@ -319,7 +318,6 @@ static void imxdma_watchdog(unsigned long data)
 
 	imx_dmav1_writel(0, DMA_CCR(channel));
 	imxdmac->internal.in_use = 0;
-	imxdmac->internal.sg = NULL;
 
 	/* Tasklet watchdog error handler */
 	tasklet_schedule(&imxdmac->dma_tasklet);
@@ -387,24 +385,23 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
 	int chno = imxdmac->channel;
 	struct imxdma_desc *desc;
 
-	if (imxdma->sg) {
-		u32 tmp;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
+	spin_lock(&imxdmac->lock);
+	if (list_empty(&imxdmac->ld_active)) {
+		spin_unlock(&imxdmac->lock);
+		goto out;
+	}
 
-			spin_lock(&imxdmac->lock);
-			if (list_empty(&imxdmac->ld_active)) {
-				spin_unlock(&imxdmac->lock);
-				goto out;
-			}
+	desc = list_first_entry(&imxdmac->ld_active,
+				struct imxdma_desc,
+				node);
+	spin_unlock(&imxdmac->lock);
 
-			desc = list_first_entry(&imxdmac->ld_active,
-						struct imxdma_desc,
-						node);
-			spin_unlock(&imxdmac->lock);
+	if (desc->sg) {
+		u32 tmp;
+		desc->sg = sg_next(desc->sg);
 
-			imxdma_sg_next(desc, imxdma->sg);
+		if (desc->sg) {
+			imxdma_sg_next(desc, desc->sg);
 
 			tmp = imx_dmav1_readl(DMA_CCR(chno));
 
@@ -477,8 +474,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Configure and enable */
 	switch (d->type) {
 	case IMXDMA_DESC_MEMCPY:
-		imxdmac->internal.sg = NULL;
-
 		imx_dmav1_writel(d->src, DMA_SAR(imxdmac->channel));
 		imx_dmav1_writel(d->dest, DMA_DAR(imxdmac->channel));
 		imx_dmav1_writel(d->config_mem | (d->config_port << 2),
@@ -494,7 +489,6 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
 	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
 	case IMXDMA_DESC_CYCLIC:
 	case IMXDMA_DESC_SLAVE_SG:
-		imxdmac->internal.sg = d->sg;
 		imxdmac->internal.resbytes = d->len;
 
 		if (d->direction == DMA_DEV_TO_MEM) {