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yaml --- r: 309783 b: refs/heads/master c: 08615d7 h: refs/heads/master i: 309781: 6998a07 309779: 3391dc4 309775: c34005c v: v3
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--- | ||
refs/heads/master: 0a4dd35c67b144d8ef9432120105f1aab9293ee9 | ||
refs/heads/master: 08615d7d85e5aa02c05bf6c4dde87d940e7f85f6 |
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What: /sys/bus/fcoe/ctlr_X | ||
Date: March 2012 | ||
KernelVersion: TBD | ||
Contact: Robert Love <robert.w.love@intel.com>, devel@open-fcoe.org | ||
Description: 'FCoE Controller' instances on the fcoe bus | ||
Attributes: | ||
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fcf_dev_loss_tmo: Device loss timeout peroid (see below). Changing | ||
this value will change the dev_loss_tmo for all | ||
FCFs discovered by this controller. | ||
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lesb_link_fail: Link Error Status Block (LESB) link failure count. | ||
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lesb_vlink_fail: Link Error Status Block (LESB) virtual link | ||
failure count. | ||
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lesb_miss_fka: Link Error Status Block (LESB) missed FCoE | ||
Initialization Protocol (FIP) Keep-Alives (FKA). | ||
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lesb_symb_err: Link Error Status Block (LESB) symbolic error count. | ||
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lesb_err_block: Link Error Status Block (LESB) block error count. | ||
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lesb_fcs_error: Link Error Status Block (LESB) Fibre Channel | ||
Serivces error count. | ||
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Notes: ctlr_X (global increment starting at 0) | ||
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What: /sys/bus/fcoe/fcf_X | ||
Date: March 2012 | ||
KernelVersion: TBD | ||
Contact: Robert Love <robert.w.love@intel.com>, devel@open-fcoe.org | ||
Description: 'FCoE FCF' instances on the fcoe bus. A FCF is a Fibre Channel | ||
Forwarder, which is a FCoE switch that can accept FCoE | ||
(Ethernet) packets, unpack them, and forward the embedded | ||
Fibre Channel frames into a FC fabric. It can also take | ||
outbound FC frames and pack them in Ethernet packets to | ||
be sent to their destination on the Ethernet segment. | ||
Attributes: | ||
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fabric_name: Identifies the fabric that the FCF services. | ||
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switch_name: Identifies the FCF. | ||
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priority: The switch's priority amongst other FCFs on the same | ||
fabric. | ||
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selected: 1 indicates that the switch has been selected for use; | ||
0 indicates that the swich will not be used. | ||
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fc_map: The Fibre Channel MAP | ||
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vfid: The Virtual Fabric ID | ||
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mac: The FCF's MAC address | ||
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fka_peroid: The FIP Keep-Alive peroid | ||
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fabric_state: The internal kernel state | ||
"Unknown" - Initialization value | ||
"Disconnected" - No link to the FCF/fabric | ||
"Connected" - Host is connected to the FCF | ||
"Deleted" - FCF is being removed from the system | ||
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dev_loss_tmo: The device loss timeout peroid for this FCF. | ||
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Notes: A device loss infrastructre similar to the FC Transport's | ||
is present in fcoe_sysfs. It is nice to have so that a | ||
link flapping adapter doesn't continually advance the count | ||
used to identify the discovered FCF. FCFs will exist in a | ||
"Disconnected" state until either the timer expires and the | ||
FCF becomes "Deleted" or the FCF is rediscovered and becomes | ||
"Connected." | ||
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Users: The first user of this interface will be the fcoeadm application, | ||
which is commonly packaged in the fcoe-utils package. |
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38 changes: 38 additions & 0 deletions
38
trunk/Documentation/devicetree/bindings/gpio/gpio-mm-lantiq.txt
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Lantiq SoC External Bus memory mapped GPIO controller | ||
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By attaching hardware latches to the EBU it is possible to create output | ||
only gpios. This driver configures a special memory address, which when | ||
written to outputs 16 bit to the latches. | ||
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The node describing the memory mapped GPIOs needs to be a child of the node | ||
describing the "lantiq,localbus". | ||
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Required properties: | ||
- compatible : Should be "lantiq,gpio-mm-lantiq" | ||
- reg : Address and length of the register set for the device | ||
- #gpio-cells : Should be two. The first cell is the pin number and | ||
the second cell is used to specify optional parameters (currently | ||
unused). | ||
- gpio-controller : Marks the device node as a gpio controller. | ||
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Optional properties: | ||
- lantiq,shadow : The default value that we shall assume as already set on the | ||
shift register cascade. | ||
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Example: | ||
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localbus@0 { | ||
#address-cells = <2>; | ||
#size-cells = <1>; | ||
ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ | ||
1 0 0x4000000 0x4000010>; /* addsel1 */ | ||
compatible = "lantiq,localbus", "simple-bus"; | ||
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gpio_mm0: gpio@4000000 { | ||
compatible = "lantiq,gpio-mm"; | ||
reg = <1 0x0 0x10>; | ||
gpio-controller; | ||
#gpio-cells = <2>; | ||
lantiq,shadow = <0x77f> | ||
}; | ||
} |
42 changes: 42 additions & 0 deletions
42
trunk/Documentation/devicetree/bindings/gpio/gpio-stp-xway.txt
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Lantiq SoC Serial To Parallel (STP) GPIO controller | ||
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The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a | ||
peripheral controller used to drive external shift register cascades. At most | ||
3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem | ||
to drive the 2 LSBs of the cascade automatically. | ||
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Required properties: | ||
- compatible : Should be "lantiq,gpio-stp-xway" | ||
- reg : Address and length of the register set for the device | ||
- #gpio-cells : Should be two. The first cell is the pin number and | ||
the second cell is used to specify optional parameters (currently | ||
unused). | ||
- gpio-controller : Marks the device node as a gpio controller. | ||
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Optional properties: | ||
- lantiq,shadow : The default value that we shall assume as already set on the | ||
shift register cascade. | ||
- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled | ||
in the shift register cascade. | ||
- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit | ||
property can enable this feature. | ||
- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. | ||
- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. | ||
- lantiq,rising : use rising instead of falling edge for the shift register | ||
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Example: | ||
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gpio1: stp@E100BB0 { | ||
compatible = "lantiq,gpio-stp-xway"; | ||
reg = <0xE100BB0 0x40>; | ||
#gpio-cells = <2>; | ||
gpio-controller; | ||
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lantiq,shadow = <0xffff>; | ||
lantiq,groups = <0x7>; | ||
lantiq,dsl = <0x3>; | ||
lantiq,phy1 = <0x7>; | ||
lantiq,phy2 = <0x7>; | ||
/* lantiq,rising; */ | ||
}; |
14 changes: 14 additions & 0 deletions
14
trunk/Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt
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NVIDIA Tegra 20 GART | ||
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Required properties: | ||
- compatible: "nvidia,tegra20-gart" | ||
- reg: Two pairs of cells specifying the physical address and size of | ||
the memory controller registers and the GART aperture respectively. | ||
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Example: | ||
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gart { | ||
compatible = "nvidia,tegra20-gart"; | ||
reg = <0x7000f024 0x00000018 /* controller registers */ | ||
0x58000000 0x02000000>; /* GART aperture */ | ||
}; |
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