---

yaml
---
r: 174537
b: refs/heads/master
c: 273fad2
h: refs/heads/master
i:
  174535: 4b92afe
v: v3

[refs]

@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c182be37ed7cb04c344501b88b8fdb747016e6cf
+refs/heads/master: 273fad2b8248e7eea8fba39555434223dd9216a4

trunk/drivers/gpu/drm/drm_fb_helper.c

@@ -707,7 +707,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
 
 		if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) {
 			mutex_lock(&dev->mode_config.mutex);
-			ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set);
+			ret = crtc->funcs->set_config(&fb_helper->crtc_info[i].mode_set);
 			mutex_unlock(&dev->mode_config.mutex);
 			if (ret)
 				return ret;

trunk/drivers/gpu/drm/radeon/atombios_crtc.c

@@ -368,14 +368,17 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 		if (encoder->crtc == crtc) {
 			radeon_encoder = to_radeon_encoder(encoder);
-			dig = radeon_encoder->enc_priv;
 			/* only enable spread spectrum on LVDS */
-			if (dig && dig->ss) {
-				percentage = dig->ss->percentage;
-				type = dig->ss->type;
-				step = dig->ss->step;
-				delay = dig->ss->delay;
-				range = dig->ss->range;
+			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
+				dig = radeon_encoder->enc_priv;
+				if (dig && dig->ss) {
+					percentage = dig->ss->percentage;
+					type = dig->ss->type;
+					step = dig->ss->step;
+					delay = dig->ss->delay;
+					range = dig->ss->range;
+				} else if (enable)
+					return;
 			} else if (enable)
 				return;
 			break;
@@ -387,7 +390,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
 
 	if (ASIC_IS_AVIVO(rdev)) {
 		memset(&args, 0, sizeof(args));
-		args.usSpreadSpectrumPercentage = percentage;
+		args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 		args.ucSpreadSpectrumType = type;
 		args.ucSpreadSpectrumStep = step;
 		args.ucSpreadSpectrumDelay = delay;
@@ -397,7 +400,7 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
 		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 	} else {
 		memset(&legacy_args, 0, sizeof(legacy_args));
-		legacy_args.usSpreadSpectrumPercentage = percentage;
+		legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
 		legacy_args.ucSpreadSpectrumType = type;
 		legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
 		legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
@@ -483,8 +486,14 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 		atom_execute_table(rdev->mode_info.atom_context,
 				   index, (uint32_t *)&adjust_pll_args);
 		adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
-	} else
-		adjusted_clock = mode->clock;
+	} else {
+		/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
+		if (ASIC_IS_AVIVO(rdev) &&
+		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
+			adjusted_clock = mode->clock * 2;
+		else
+			adjusted_clock = mode->clock;
+	}
 
 	if (radeon_crtc->crtc_id == 0)
 		pll = &rdev->clock.p1pll;

trunk/drivers/gpu/drm/radeon/radeon_atombios.c

@@ -655,6 +655,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
 				p1pll->pll_out_min = 64800;
 			else
 				p1pll->pll_out_min = 20000;
+		} else if (p1pll->pll_out_min > 64800) {
+			/* Limiting the pll output range is a good thing generally as
+			 * it limits the number of possible pll combinations for a given
+			 * frequency presumably to the ones that work best on each card.
+			 * However, certain duallink DVI monitors seem to like
+			 * pll combinations that would be limited by this at least on
+			 * pre-DCE 3.0 r6xx hardware.  This might need to be adjusted per
+			 * family.
+			 */
+			p1pll->pll_out_min = 64800;
 		}
 
 		p1pll->pll_in_min =

trunk/drivers/gpu/drm/radeon/radeon_combios.c

@@ -1587,6 +1587,12 @@ static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
 	    dev->pdev->subsystem_device == 0x009f)
 		return false;
 
+	/* HP dc5750 has non-existent TV port */
+	if (dev->pdev->device == 0x5974 &&
+	    dev->pdev->subsystem_vendor == 0x103c &&
+	    dev->pdev->subsystem_device == 0x280a)
+		return false;
+
 	return true;
 }
 

trunk/drivers/gpu/drm/radeon/radeon_device.c

@@ -443,27 +443,32 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 	return r;
 }
 
-static struct card_info atom_card_info = {
-	.dev = NULL,
-	.reg_read = cail_reg_read,
-	.reg_write = cail_reg_write,
-	.mc_read = cail_mc_read,
-	.mc_write = cail_mc_write,
-	.pll_read = cail_pll_read,
-	.pll_write = cail_pll_write,
-};
-
 int radeon_atombios_init(struct radeon_device *rdev)
 {
-	atom_card_info.dev = rdev->ddev;
-	rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
+	struct card_info *atom_card_info =
+	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
+
+	if (!atom_card_info)
+		return -ENOMEM;
+
+	rdev->mode_info.atom_card_info = atom_card_info;
+	atom_card_info->dev = rdev->ddev;
+	atom_card_info->reg_read = cail_reg_read;
+	atom_card_info->reg_write = cail_reg_write;
+	atom_card_info->mc_read = cail_mc_read;
+	atom_card_info->mc_write = cail_mc_write;
+	atom_card_info->pll_read = cail_pll_read;
+	atom_card_info->pll_write = cail_pll_write;
+
+	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
 	radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
 	return 0;
 }
 
 void radeon_atombios_fini(struct radeon_device *rdev)
 {
 	kfree(rdev->mode_info.atom_context);
+	kfree(rdev->mode_info.atom_card_info);
 }
 
 int radeon_combios_init(struct radeon_device *rdev)

trunk/drivers/gpu/drm/radeon/radeon_mode.h

@@ -172,6 +172,7 @@ enum radeon_connector_table {
 
 struct radeon_mode_info {
 	struct atom_context *atom_context;
+	struct card_info *atom_card_info;
 	enum radeon_connector_table connector_table;
 	bool mode_config_initialized;
 	struct radeon_crtc *crtcs[2];

trunk/drivers/gpu/drm/radeon/rs400.c

@@ -418,6 +418,8 @@ int rs400_resume(struct radeon_device *rdev)
 	rs400_gart_disable(rdev);
 	/* Resume clock before doing reset */
 	r300_clock_startup(rdev);
+	/* setup MC before calling post tables */
+	rs400_mc_program(rdev);
 	/* Reset gpu before posting otherwise ATOM will enter infinite loop */
 	if (radeon_gpu_reset(rdev)) {
 		dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",